abejgonzalez
978832df93
added bootrom symlink to support rocket
2019-04-23 11:53:18 -07:00
abejgonzalez
862c217ff4
allow rocket builds | asm tests pass
2019-04-23 11:50:36 -07:00
abejgonzalez
c1a0916e40
add asm/bmark tests to generator
2019-04-23 09:20:47 -07:00
abejgonzalez
0e5e1bac15
fix test harness builds
2019-04-22 22:36:04 -07:00
abejgonzalez
f11901a393
added configmixin file
2019-04-22 16:41:11 -07:00
abejgonzalez
0278845009
separated mixins from configs
2019-04-22 16:28:37 -07:00
abejgonzalez
47149a0649
change smallboom to boomconfig
2019-04-22 14:47:53 -07:00
abejgonzalez
180a2ab4a8
harness builds with gpio tied off
2019-04-21 16:07:30 -07:00
abejgonzalez
668047e3fd
added GPIO config | breaks on building test harness
2019-04-21 15:19:15 -07:00
abejgonzalez
eda0b113c1
more default subprojects | fix example builds
2019-04-21 14:41:02 -07:00
abejgonzalez
b8eadb99eb
add back example to rocket system
2019-04-20 21:20:20 -07:00
abejgonzalez
c0b0e293c5
removed boom package and combined into example | removed example from naming | split generator file
2019-04-20 21:18:20 -07:00
abejgonzalez
e9ed53424b
add sifive blocks | add rebar configs for boom
2019-04-19 21:06:32 -07:00
abejgonzalez
885c5f74db
bump boom/firrtl | support building boom | update genfiles in simulator to make rv32 bootrom | misc cleanup
2019-04-17 17:08:08 -07:00
abejgonzalez
7d887b212c
align rebar with tip of project-template master | fixes build issues
2019-04-17 16:02:44 -07:00
Colin Schmidt
17c38a502a
Help people who want to run tests ( #50 )
...
* Help people who want to run tests
* Include generated makefrags for simulation
2019-03-11 11:26:27 -07:00
Paul Rigge
61d1798888
Fix AXI4 example.
...
I accidentally stumbled into a working AXI4 configuration by multiplying
pbus.beatBytes by 8, but it was fragile. This is the "right way" to add
an AXI4 peripheral.
2019-03-07 20:58:23 -08:00
Paul Rigge
bf23d7aa6c
Fix VCS build.
...
VCS doesn't use the same arguments for C headers that verilator uses.
Generate the dot-f file differently for the different simulators.
2019-03-06 23:06:24 -08:00
Paul Rigge
8a522ba404
Fix some build system problems.
...
1) Bump testchipip to include forgotten commit
2) Add some support for generating VCS files
3) Fix some makefile deps
2019-03-06 22:10:31 -08:00
Paul Rigge
ddf3159d61
Bump rocket, make possible to use published deps ( #47 )
...
* Use published rocketchip
* Simulator works!
* Gitignore was masking csrc
* Fix broken submodules
* Update gitignore
* Fix things up
* Some more cleanup
* Clean up so that using maven works
* Incorporate feedback
* Oops
* Add workaround for some of csrc
* Forgot dtm and jtag
* Make name better and add comment
* Extraneous comment
* Fix includes.
After running a clean build, I realized old build state was masking this
problem. verisim/csrc needs to be in the include path until we find a more
permanent solution to our problem.
* Add target to generate verilator-specific files.
* Ignore DS_Store
* Generate bootrom from testchipip
* Oops
* Add extraneous rocket-dsptools reference
2019-03-06 18:22:21 -08:00
Paul Rigge
8cf06db45c
Add an AXI4 flavor of PWM peripheral.
...
Also closes #41 .
2019-01-24 17:13:40 -08:00
Edward Wang
d48587b671
Update project-template for testchipip master
2018-11-02 12:05:36 -07:00
Albert Ou
220aeea4c8
Bump rocket-chip
...
- Update Scala version to 2.12.4; work around SBT multi-project idiosyncrasies
- Remove HasSystemErrorSlave
2018-09-29 13:30:07 -07:00
Howard Mao
4c8c6e29f0
update rocket-chip again
2018-04-18 17:13:07 -07:00
Howard Mao
7dc738a831
DualCoreConfig should be actually dual core
2018-04-17 16:06:44 -07:00
Howard Mao
7e70e3525f
move bootrom to testchipip
2018-04-17 15:13:47 -07:00
Howard Mao
28539dc562
bump rocket-chip to March commit
2018-04-16 19:33:51 -07:00
Howard Mao
073c16961e
make sure annotations are generated and carried through to verilog elaboration
2018-02-23 11:50:33 -08:00
Howard Mao
eaff48e312
fix issue #20 : PWMConfig elaboration error due to requirement failure
2018-02-23 10:54:05 -08:00
Donggyu Kim
ed13397967
changes for new rocket-chip
2018-01-15 16:07:44 -08:00
Howard Mao
e4a4046375
get RV32 working
2017-11-03 18:00:27 -07:00
Howard Mao
5c200ddb6e
bump rocket-chip and testchipip
2017-10-26 13:20:13 -07:00
Howard Mao
4dd2d5f881
have core 0 interrupt other cores
2017-09-12 20:33:36 -07:00
Howard Mao
506afbb363
bump rocket-chip for flattened coreplex/system
2017-08-31 14:35:13 -07:00
Howard Mao
cb79078641
get rid of tlserdes project
2017-08-31 14:34:35 -07:00
Howard Mao
91df4098f3
remove SimpleNIC
2017-08-31 11:06:41 -07:00
Howard Mao
f28f2379a4
SerialInterfaceWidth is not actually configurable
2017-07-21 06:12:25 +00:00
Howard Mao
ada96f3724
update verilator so that plusarg_reader works
2017-07-20 20:19:02 +00:00
Howard Mao
6175249845
add project using a SERDES memory
2017-07-18 20:25:32 -07:00
Howard Mao
752a28893d
test multi-channel memory
2017-07-18 20:25:32 -07:00
Howard Mao
984827db2e
update rocketchip
2017-07-12 10:44:27 -07:00
Howard Mao
cb6290539c
add network simulation C++ code
2017-07-01 19:58:31 -07:00
Howard Mao
6e3a173c93
add SimpleNic
2017-06-26 20:27:47 -07:00
Howard Mao
f766dcc550
merge the different ExampleTop subclasses into the example package
2017-06-26 16:29:04 -07:00
Howard Mao
31f5fc98e4
fix multi-tracker block device
2017-06-23 22:50:54 -07:00
Howard Mao
119e563ea6
fix verilator build
2017-06-22 17:41:48 -07:00
Howard Mao
9a9ebea207
add new (Tilelink2) RoCC accelerator interface
...
Includes configuration, test programs, and documentation updates.
2017-06-22 16:43:14 -07:00
Howard Mao
a1d866c344
fix chisel3 deprecations
2017-06-22 10:04:47 -07:00
Howard Mao
bac811a173
add ExampleTopWithBlockDevice and tests
2017-06-21 11:09:55 -07:00
Howard Mao
1f3e892b64
update to latest rocket-chip
2017-06-21 11:05:40 -07:00
