update to latest rocket-chip
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Submodule rocket-chip updated: 274d908d98...0fdaa28694
@@ -14,13 +14,8 @@ class TestHarness(implicit val p: Parameters) extends Module {
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def buildTop(p: Parameters): ExampleTop = LazyModule(new ExampleTop()(p))
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val dut = Module(buildTop(p).module)
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val ser = Module(new SimSerialWrapper(p(SerialInterfaceWidth)))
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val nMemChannels = p(coreplex.BankedL2Config).nMemoryChannels
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val mem = Module(LazyModule(new SimAXIMem(nMemChannels)).module)
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mem.io.axi4 <> dut.io.mem_axi4
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ser.io.serial <> dut.io.serial
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io.success := ser.io.exit
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dut.connectSimAXIMem()
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io.success := dut.connectSimSerial()
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}
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object Generator extends GeneratorApp {
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@@ -5,34 +5,22 @@ import config.Parameters
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import testchipip._
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import rocketchip._
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class ExampleTop(implicit p: Parameters) extends BaseTop()(p)
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with PeripheryMasterAXI4Mem
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with PeripheryBootROM
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with PeripheryZero
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with PeripheryCounter
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with HardwiredResetVector
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with RocketPlexMaster
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with NoDebug
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with PeripherySerial {
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override lazy val module = new ExampleTopModule(this, () => new ExampleTopBundle(this))
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class ExampleTop(implicit p: Parameters) extends BaseSystem
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with HasPeripheryMasterAXI4MemPort
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with HasPeripheryErrorSlave
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with HasPeripheryZeroSlave
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with HasPeripheryBootROM
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with HasPeripheryRTCCounter
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with HasRocketPlexMaster
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with HasNoDebug
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with HasPeripherySerial {
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override lazy val module = new ExampleTopModule(this)
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}
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class ExampleTopBundle[+L <: ExampleTop](l: L) extends BaseTopBundle(l)
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with PeripheryMasterAXI4MemBundle
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with PeripheryBootROMBundle
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with PeripheryZeroBundle
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with PeripheryCounterBundle
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with HardwiredResetVectorBundle
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with RocketPlexMasterBundle
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with PeripherySerialBundle
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class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](l: L, b: () => B)
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extends BaseTopModule(l, b)
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with PeripheryMasterAXI4MemModule
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with PeripheryBootROMModule
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with PeripheryZeroModule
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with PeripheryCounterModule
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with HardwiredResetVectorModule
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with RocketPlexMasterModule
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with NoDebugModule
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with PeripherySerialModule
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class ExampleTopModule[+L <: ExampleTop](l: L) extends BaseSystemModule(l)
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with HasPeripheryMasterAXI4MemPortModuleImp
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with HasPeripheryBootROMModuleImp
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with HasPeripheryRTCCounterModuleImp
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with HasRocketPlexMasterModuleImp
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with HasNoDebugModuleImp
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with HasPeripherySerialModuleImp
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@@ -76,9 +76,8 @@ class PWMTL(c: PWMParams)(implicit p: Parameters)
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new TLRegBundle(c, _) with PWMTLBundle)(
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new TLRegModule(c, _, _) with PWMTLModule)
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trait PeripheryPWM extends LazyModule with HasPeripheryParameters {
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trait HasPeripheryPWM extends HasSystemNetworks {
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implicit val p: Parameters
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val peripheryBus: TLXbar
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private val address = 0x2000
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@@ -89,14 +88,11 @@ trait PeripheryPWM extends LazyModule with HasPeripheryParameters {
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peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
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}
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trait PeripheryPWMBundle {
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val pwmout = Output(Bool())
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}
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trait PeripheryPWMModule extends HasPeripheryParameters {
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trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp {
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implicit val p: Parameters
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val io: PeripheryPWMBundle
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val outer: PeripheryPWM
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val outer: HasPeripheryPWM
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io.pwmout := outer.pwm.module.io.pwmout
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val pwmout = IO(Output(Bool()))
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pwmout := outer.pwm.module.io.pwmout
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}
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@@ -4,14 +4,10 @@ import chisel3._
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import example._
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import config.Parameters
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class ExampleTopWithPWM(implicit p: Parameters) extends ExampleTop()(p)
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with PeripheryPWM {
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override lazy val module = new ExampleTopWithPWMModule(this, () => new ExampleTopWithPWMBundle(this))
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class ExampleTopWithPWM(implicit p: Parameters) extends ExampleTop
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with HasPeripheryPWM {
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override lazy val module = new ExampleTopWithPWMModule(this)
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}
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class ExampleTopWithPWMBundle[+L <: ExampleTopWithPWM](l: L)
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extends ExampleTopBundle(l)
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with PeripheryPWMBundle
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class ExampleTopWithPWMModule[+L <: ExampleTopWithPWM, +B <: ExampleTopWithPWMBundle[L]](l: L, b: () => B)
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extends ExampleTopModule(l, b) with PeripheryPWMModule
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class ExampleTopWithPWMModule(l: ExampleTopWithPWM)
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extends ExampleTopModule(l) with HasPeripheryPWMModuleImp
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Submodule testchipip updated: 8bd439f37b...2e9301c190
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