Update project-template for testchipip master

Makefrag

@@ -25,7 +25,7 @@ include $(testchip_dir)/Makefrag
 CHISEL_ARGS ?=
 
 FIRRTL_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).fir
-ANNO_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).anno
+ANNO_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).anno.json
 VERILOG_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).v
 
 $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(bootrom_img) $(FIRRTL_JAR)

src/main/scala/example/TestHarness.scala

@@ -3,7 +3,7 @@ package example
 import chisel3._
 import freechips.rocketchip.diplomacy.LazyModule
 import freechips.rocketchip.config.{Field, Parameters}
-import testchipip.GeneratorApp
+import freechips.rocketchip.util.GeneratorApp
 
 case object BuildTop extends Field[(Clock, Bool, Parameters) => ExampleTopModule[ExampleTop]]
 
@@ -21,6 +21,7 @@ class TestHarness(implicit val p: Parameters) extends Module {
 }
 
 object Generator extends GeneratorApp {
+  val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
   generateFirrtl
   generateAnno
 }