get RV32 working

This commit is contained in:
Howard Mao
2017-11-03 18:00:27 -07:00
parent 52068497c4
commit e4a4046375
6 changed files with 24 additions and 8 deletions

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@@ -32,7 +32,7 @@ $(FIRRTL_JAR): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)/firrtl/src/main/scala
build_dir=$(sim_dir)/generated-src
bootrom_img = $(base_dir)/bootrom/bootrom.img
bootrom_img = $(base_dir)/bootrom/bootrom.rv64.img $(base_dir)/bootrom/bootrom.rv32.img
CHISEL_ARGS ?=

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@@ -1,7 +1,9 @@
bootrom_img = bootrom.img
bootrom_dump = bootrom.dump
bootrom_img = bootrom.rv64.img bootrom.rv32.img
bootrom_dump = bootrom.rv64.dump bootrom.rv32.dump
GCC=riscv64-unknown-elf-gcc -march=rv64imafd
GCC=riscv64-unknown-elf-gcc
CFLAGS_RV64=-mabi=lp64 -march=rv64ima
CFLAGS_RV32=-mabi=ilp32 -march=rv32ima
OBJCOPY=riscv64-unknown-elf-objcopy
OBJDUMP=riscv64-unknown-elf-objdump
@@ -12,8 +14,11 @@ dump: $(bootrom_dump)
%.img: %.elf
$(OBJCOPY) -O binary --change-addresses=-0x10000 $< $@
%.elf: %.S linker.ld
$(GCC) -Tlinker.ld $< -nostdlib -static -o $@
%.rv32.elf: %.S linker.ld
$(GCC) $(CFLAGS_RV32) -Tlinker.ld $< -nostdlib -static -o $@
%.rv64.elf: %.S linker.ld
$(GCC) $(CFLAGS_RV64) -Tlinker.ld $< -nostdlib -static -o $@
%.dump: %.elf
$(OBJDUMP) -d $< > $@

BIN
bootrom/bootrom.rv32.img Executable file

Binary file not shown.

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@@ -2,10 +2,17 @@ package example
import chisel3._
import freechips.rocketchip.config.{Parameters, Config}
import freechips.rocketchip.coreplex.{WithRoccExample, WithNMemoryChannels, WithNBigCores}
import freechips.rocketchip.coreplex.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32}
import freechips.rocketchip.devices.tilelink.BootROMParams
import freechips.rocketchip.diplomacy.LazyModule
import freechips.rocketchip.tile.XLen
import testchipip._
class WithBootROM extends Config((site, here, up) => {
case BootROMParams => BootROMParams(
contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img")
})
class WithExampleTop extends Config((site, here, up) => {
case BuildTop => (clock: Clock, reset: Bool, p: Parameters) =>
Module(LazyModule(new ExampleTop()(p)).module)
@@ -33,6 +40,7 @@ class WithSimBlockDevice extends Config((site, here, up) => {
})
class BaseExampleConfig extends Config(
new WithBootROM ++
new freechips.rocketchip.system.DefaultConfig)
class DefaultExampleConfig extends Config(
@@ -58,3 +66,6 @@ class WithFourMemChannels extends WithNMemoryChannels(4)
class DualCoreConfig extends Config(
// Core gets tacked onto existing list
new WithNBigCores(1) ++ new DefaultExampleConfig)
class RV32ExampleConfig extends Config(
new WithRV32 ++ new DefaultExampleConfig)