get RV32 working
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2
Makefrag
2
Makefrag
@@ -32,7 +32,7 @@ $(FIRRTL_JAR): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)/firrtl/src/main/scala
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build_dir=$(sim_dir)/generated-src
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bootrom_img = $(base_dir)/bootrom/bootrom.img
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bootrom_img = $(base_dir)/bootrom/bootrom.rv64.img $(base_dir)/bootrom/bootrom.rv32.img
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CHISEL_ARGS ?=
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@@ -1,7 +1,9 @@
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bootrom_img = bootrom.img
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bootrom_dump = bootrom.dump
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bootrom_img = bootrom.rv64.img bootrom.rv32.img
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bootrom_dump = bootrom.rv64.dump bootrom.rv32.dump
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GCC=riscv64-unknown-elf-gcc -march=rv64imafd
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GCC=riscv64-unknown-elf-gcc
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CFLAGS_RV64=-mabi=lp64 -march=rv64ima
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CFLAGS_RV32=-mabi=ilp32 -march=rv32ima
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OBJCOPY=riscv64-unknown-elf-objcopy
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OBJDUMP=riscv64-unknown-elf-objdump
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@@ -12,8 +14,11 @@ dump: $(bootrom_dump)
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%.img: %.elf
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$(OBJCOPY) -O binary --change-addresses=-0x10000 $< $@
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%.elf: %.S linker.ld
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$(GCC) -Tlinker.ld $< -nostdlib -static -o $@
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%.rv32.elf: %.S linker.ld
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$(GCC) $(CFLAGS_RV32) -Tlinker.ld $< -nostdlib -static -o $@
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%.rv64.elf: %.S linker.ld
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$(GCC) $(CFLAGS_RV64) -Tlinker.ld $< -nostdlib -static -o $@
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%.dump: %.elf
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$(OBJDUMP) -d $< > $@
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BIN
bootrom/bootrom.rv32.img
Executable file
BIN
bootrom/bootrom.rv32.img
Executable file
Binary file not shown.
@@ -2,10 +2,17 @@ package example
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import chisel3._
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import freechips.rocketchip.config.{Parameters, Config}
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import freechips.rocketchip.coreplex.{WithRoccExample, WithNMemoryChannels, WithNBigCores}
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import freechips.rocketchip.coreplex.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32}
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import freechips.rocketchip.devices.tilelink.BootROMParams
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import freechips.rocketchip.diplomacy.LazyModule
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import freechips.rocketchip.tile.XLen
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import testchipip._
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class WithBootROM extends Config((site, here, up) => {
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case BootROMParams => BootROMParams(
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contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img")
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})
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class WithExampleTop extends Config((site, here, up) => {
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case BuildTop => (clock: Clock, reset: Bool, p: Parameters) =>
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Module(LazyModule(new ExampleTop()(p)).module)
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@@ -33,6 +40,7 @@ class WithSimBlockDevice extends Config((site, here, up) => {
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})
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class BaseExampleConfig extends Config(
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new WithBootROM ++
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new freechips.rocketchip.system.DefaultConfig)
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class DefaultExampleConfig extends Config(
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@@ -58,3 +66,6 @@ class WithFourMemChannels extends WithNMemoryChannels(4)
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class DualCoreConfig extends Config(
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// Core gets tacked onto existing list
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new WithNBigCores(1) ++ new DefaultExampleConfig)
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class RV32ExampleConfig extends Config(
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new WithRV32 ++ new DefaultExampleConfig)
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Submodule testchipip updated: 9dd1e3a516...3fe8806890
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