update rocketchip

src/main/scala/example/Configs.scala

@@ -1,10 +1,10 @@
 package example
 
 import chisel3._
-import config.{Parameters, Config}
-import diplomacy.LazyModule
-import coreplex.WithRoccExample
-import rocketchip.WithoutTLMonitors
+import freechips.rocketchip.chip.WithoutTLMonitors
+import freechips.rocketchip.config.{Parameters, Config}
+import freechips.rocketchip.coreplex.WithRoccExample
+import freechips.rocketchip.diplomacy.LazyModule
 import testchipip._
 
 class WithExampleTop extends Config((site, here, up) => {
@@ -52,7 +52,7 @@ class WithSimNetwork extends Config((site, here, up) => {
 class BaseExampleConfig extends Config(
   new WithoutTLMonitors ++
   new WithSerialAdapter ++
-  new rocketchip.DefaultConfig)
+  new freechips.rocketchip.chip.DefaultConfig)
 
 class DefaultExampleConfig extends Config(
   new WithExampleTop ++ new BaseExampleConfig)

src/main/scala/example/PWM.scala

@@ -2,14 +2,12 @@ package example
 
 import chisel3._
 import chisel3.util._
-import config.{Parameters, Field}
-import uncore.tilelink._
-import uncore.tilelink2._
-import junctions._
-import diplomacy._
-import regmapper.{HasRegMap, RegField}
-import rocketchip._
-import _root_.util.UIntIsOneOf
+import freechips.rocketchip.config.{Parameters, Field}
+import freechips.rocketchip.chip._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.regmapper.{HasRegMap, RegField}
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util.UIntIsOneOf
 
 case class PWMParams(address: BigInt, beatBytes: Int)
 

src/main/scala/example/TestHarness.scala

@@ -1,10 +1,9 @@
 package example
 
-import diplomacy.LazyModule
-import rocketchip._
-import testchipip._
 import chisel3._
-import config.{Field, Parameters}
+import freechips.rocketchip.diplomacy.LazyModule
+import freechips.rocketchip.config.{Field, Parameters}
+import testchipip.GeneratorApp
 
 case object BuildTop extends Field[Parameters => ExampleTopModule[ExampleTop]]
 

src/main/scala/example/Top.scala

@@ -1,9 +1,9 @@
 package example
 
 import chisel3._
-import config.Parameters
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.chip._
 import testchipip._
-import rocketchip._
 
 class ExampleTop(implicit p: Parameters) extends BaseSystem
     with HasPeripheryMasterAXI4MemPort