bump rocket-chip and testchipip

src/main/scala/example/Configs.scala

@@ -7,17 +7,17 @@ import freechips.rocketchip.diplomacy.LazyModule
 import testchipip._
 
 class WithExampleTop extends Config((site, here, up) => {
-  case BuildTop => (p: Parameters) =>
+  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) =>
     Module(LazyModule(new ExampleTop()(p)).module)
 })
 
 class WithPWM extends Config((site, here, up) => {
-  case BuildTop => (p: Parameters) =>
+  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) =>
     Module(LazyModule(new ExampleTopWithPWM()(p)).module)
 })
 
 class WithBlockDeviceModel extends Config((site, here, up) => {
-  case BuildTop => (p: Parameters) => {
+  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
     val top = Module(LazyModule(new ExampleTopWithBlockDevice()(p)).module)
     top.connectBlockDeviceModel()
     top
@@ -25,9 +25,9 @@ class WithBlockDeviceModel extends Config((site, here, up) => {
 })
 
 class WithSimBlockDevice extends Config((site, here, up) => {
-  case BuildTop => (p: Parameters) => {
+  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
     val top = Module(LazyModule(new ExampleTopWithBlockDevice()(p)).module)
-    top.connectSimBlockDevice()
+    top.connectSimBlockDevice(clock, reset)
     top
   }
 })

src/main/scala/example/PWM.scala

@@ -37,7 +37,7 @@ trait PWMTLBundle extends Bundle {
   val pwmout = Output(Bool())
 }
 
-trait PWMTLModule extends Module with HasRegMap {
+trait PWMTLModule extends HasRegMap {
   val io: PWMTLBundle
   implicit val p: Parameters
   def params: PWMParams
@@ -85,7 +85,7 @@ trait HasPeripheryPWM extends HasPeripheryBus {
   pwm.node := pbus.toVariableWidthSlaves
 }
 
-trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp {
+trait HasPeripheryPWMModuleImp extends LazyModuleImp {
   implicit val p: Parameters
   val outer: HasPeripheryPWM
 

src/main/scala/example/TestHarness.scala

@@ -5,14 +5,14 @@ import freechips.rocketchip.diplomacy.LazyModule
 import freechips.rocketchip.config.{Field, Parameters}
 import testchipip.GeneratorApp
 
-case object BuildTop extends Field[Parameters => ExampleTopModule[ExampleTop]]
+case object BuildTop extends Field[(Clock, Bool, Parameters) => ExampleTopModule[ExampleTop]]
 
 class TestHarness(implicit val p: Parameters) extends Module {
   val io = IO(new Bundle {
     val success = Output(Bool())
   })
 
-  val dut = p(BuildTop)(p)
+  val dut = p(BuildTop)(clock, reset.toBool, p)
   dut.connectSimAXIMem()
   io.success := dut.connectSimSerial()
 }

src/main/scala/example/Top.scala

@@ -9,7 +9,7 @@ import testchipip._
 class ExampleTop(implicit p: Parameters) extends RocketCoreplex
     with HasMasterAXI4MemPort
     with HasPeripheryBootROM
-    with HasPeripheryErrorSlave
+    with HasSystemErrorSlave
     with HasNoDebug
     with HasPeripherySerial {
   override lazy val module = new ExampleTopModule(this)