add network simulation C++ code

src/main/scala/example/Configs.scala

@@ -33,7 +33,7 @@ class WithSimBlockDevice extends Config((site, here, up) => {
   }
 })
 
-class WithSimpleNIC extends Config((site, here, up) => {
+class WithLoopbackNIC extends Config((site, here, up) => {
   case BuildTop => (p: Parameters) => {
     val top = Module(LazyModule(new ExampleTopWithSimpleNIC()(p)).module)
     top.connectNicLoopback()
@@ -41,6 +41,14 @@ class WithSimpleNIC extends Config((site, here, up) => {
   }
 })
 
+class WithSimNetwork extends Config((site, here, up) => {
+  case BuildTop => (p: Parameters) => {
+    val top = Module(LazyModule(new ExampleTopWithSimpleNIC()(p)).module)
+    top.connectSimNetwork()
+    top
+  }
+})
+
 class BaseExampleConfig extends Config(
   new WithoutTLMonitors ++
   new WithSerialAdapter ++
@@ -60,8 +68,11 @@ class SimBlockDeviceConfig extends Config(
 class BlockDeviceModelConfig extends Config(
   new WithBlockDevice ++ new WithBlockDeviceModel ++ new BaseExampleConfig)
 
-class SimpleNICConfig extends Config(
-  new WithSimpleNIC ++ new BaseExampleConfig)
+class LoopbackNICConfig extends Config(
+  new WithLoopbackNIC ++ new BaseExampleConfig)
+
+class SimNetworkConfig extends Config(
+  new WithSimNetwork ++ new BaseExampleConfig)
 
 class WithTwoTrackers extends WithNBlockDeviceTrackers(2)
 class WithFourTrackers extends WithNBlockDeviceTrackers(4)

verisim/Makefile

@@ -25,14 +25,16 @@ long_name = $(PROJECT).$(MODEL).$(CONFIG)
 sim_vsrcs = \
 	$(build_dir)/$(long_name).v \
 	$(base_dir)/rocket-chip/vsrc/AsyncResetReg.v \
-	$(base_dir)/rocket-chip/vsrc/plusarg_reader.v \
 	$(base_dir)/testchipip/vsrc/SimSerial.v \
-	$(base_dir)/testchipip/vsrc/SimBlockDevice.v
+	$(base_dir)/testchipip/vsrc/SimBlockDevice.v \
+	$(base_dir)/testchipip/vsrc/SimNetwork.v
 
 sim_csrcs = \
 	$(base_dir)/testchipip/csrc/SimSerial.cc \
 	$(base_dir)/testchipip/csrc/SimBlockDevice.cc \
+	$(base_dir)/testchipip/csrc/SimNetwork.cc \
 	$(base_dir)/testchipip/csrc/blkdev.cc \
+	$(base_dir)/testchipip/csrc/network.cc \
 	$(base_dir)/testchipip/csrc/verilator-harness.cc
 
 model_dir = $(build_dir)/$(long_name)

vsim/Makefile

@@ -23,11 +23,14 @@ sim_vsrcs = \
 	$(base_dir)/rocket-chip/vsrc/plusarg_reader.v \
 	$(base_dir)/testchipip/vsrc/SimSerial.v \
 	$(base_dir)/testchipip/vsrc/SimBlockDevice.v \
+	$(base_dir)/testchipip/vsrc/SimNetwork.v \
 
 sim_csrcs = \
 	$(base_dir)/testchipip/csrc/SimSerial.cc \
 	$(base_dir)/testchipip/csrc/SimBlockDevice.cc \
+	$(base_dir)/testchipip/csrc/SimNetwork.cc \
 	$(base_dir)/testchipip/csrc/blkdev.cc \
+	$(base_dir)/testchipip/csrc/network.cc \
 
 VCS = vcs -full64