move bootrom to testchipip

Makefrag

@@ -31,8 +31,9 @@ $(FIRRTL_JAR): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)/firrtl/src/main/scala
 	cp -p $(FIRRTL_JAR) $(ROCKETCHIP_DIR)/lib
 
 build_dir=$(sim_dir)/generated-src
+testchip_dir = $(base_dir)/testchipip
 
-bootrom_img = $(base_dir)/bootrom/bootrom.rv64.img $(base_dir)/bootrom/bootrom.rv32.img
+include $(testchip_dir)/Makefrag
 
 CHISEL_ARGS ?=
 

bootrom/.gitignore

@@ -1,2 +0,0 @@
-*.elf
-*.dump

bootrom/Makefile

@@ -1,27 +0,0 @@
-bootrom_img = bootrom.rv64.img bootrom.rv32.img
-bootrom_dump = bootrom.rv64.dump bootrom.rv32.dump
-
-GCC=riscv64-unknown-elf-gcc
-CFLAGS_RV64=-mabi=lp64 -march=rv64ima
-CFLAGS_RV32=-mabi=ilp32 -march=rv32ima
-OBJCOPY=riscv64-unknown-elf-objcopy
-OBJDUMP=riscv64-unknown-elf-objdump
-
-img: $(bootrom_img)
-
-dump: $(bootrom_dump)
-
-%.img: %.elf
-	$(OBJCOPY) -O binary --change-addresses=-0x10000 $< $@
-
-%.rv32.elf: %.S linker.ld
-	$(GCC) $(CFLAGS_RV32) -Tlinker.ld $< -nostdlib -static -o $@
-
-%.rv64.elf: %.S linker.ld
-	$(GCC) $(CFLAGS_RV64) -Tlinker.ld $< -nostdlib -static -o $@
-
-%.dump: %.elf
-	$(OBJDUMP) -d $< > $@
-
-clean:
-	rm -f *.elf *.dump *.img

bootrom/bootrom.S

@@ -1,46 +0,0 @@
-#define DRAM_BASE 0x80000000
-
-.section .text.start, "ax", @progbits
-.globl _start
-_start:
-  li a1, 0x2000000 // base address of clint
-  csrr a0, mhartid
-  bnez a0, boot_core
-
-  addi a2, a1, 4
-  li a3, 1
-interrupt_loop:
-  sw a3, 0(a2)
-  addi a2, a2, 4
-  lw a3, -4(a2)
-  bnez a3, interrupt_loop
-  j boot_core
-
-.section .text.hang, "ax", @progbits
-.globl _hang
-_hang:
-  // This boot ROM doesn't know about any boot devices, so it just spins,
-  // waiting for the serial interface to load the program and interrupt it
-  la a0, _start
-  csrw mtvec, a0
-  li a0, 8 // MIE or MSIP bit
-  csrw mie, a0 // set only MSIP in mie CSR
-  csrw mideleg, zero // no delegation
-  csrs mstatus, a0 // set MIE in mstatus CSR
-wfi_loop:
-  wfi
-  j wfi_loop
-
-boot_core:
-  sll a0, a0, 2 // offset for hart msip
-  add a0, a0, a1
-  sw zero, 0(a0) // clear the interrupt
-  li a0, DRAM_BASE // program reset vector
-  csrw mepc, a0 // return from interrupt to start of user program
-  csrr a0, mhartid // hartid for next level bootloader
-  la a1, _dtb // dtb address for next level bootloader
-  li a2, 0x80 // set mstatus MPIE to 0
-  csrc mstatus, a2
-  mret
-
-_dtb:

bootrom/linker.ld

@@ -1,9 +0,0 @@
-SECTIONS
-{
-    ROM_BASE = 0x10000; /* ... but actually position independent */
-
-    . = ROM_BASE;
-    .text.start : { *(.text.start) }
-    . = ROM_BASE + 0x40;
-    .text.hang : { *(.text.hang) }
-}

src/main/scala/example/Configs.scala

@@ -10,7 +10,7 @@ import testchipip._
 
 class WithBootROM extends Config((site, here, up) => {
   case BootROMParams => BootROMParams(
-    contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img")
+    contentFileName = s"./testchipip/bootrom/bootrom.rv${site(XLen)}.img")
 })
 
 object ConfigValName {

verisim/Makefile

@@ -24,15 +24,12 @@ long_name = $(PROJECT).$(MODEL).$(CONFIG)
 
 sim_vsrcs = \
 	$(build_dir)/$(long_name).v \
-	$(base_dir)/rocket-chip/vsrc/AsyncResetReg.v \
-	$(base_dir)/testchipip/vsrc/SimSerial.v \
-	$(base_dir)/testchipip/vsrc/SimBlockDevice.v \
+	$(ROCKETCHIP_DIR)/vsrc/AsyncResetReg.v \
+	$(testchip_vsrcs)
 
 sim_csrcs = \
-	$(base_dir)/testchipip/csrc/SimSerial.cc \
-	$(base_dir)/testchipip/csrc/SimBlockDevice.cc \
-	$(base_dir)/testchipip/csrc/blkdev.cc \
-	$(base_dir)/testchipip/csrc/verilator-harness.cc
+	$(testchip_dir)/csrc/verilator-harness.cc \
+	$(testchip_csrcs)
 
 model_dir = $(build_dir)/$(long_name)
 model_dir_debug = $(build_dir)/$(long_name).debug

vsim/Makefile

@@ -18,16 +18,13 @@ include $(base_dir)/Makefrag
 
 sim_vsrcs = \
 	$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).v \
-	$(base_dir)/rocket-chip/vsrc/TestDriver.v \
-	$(base_dir)/rocket-chip/vsrc/AsyncResetReg.v \
-	$(base_dir)/rocket-chip/vsrc/plusarg_reader.v \
-	$(base_dir)/testchipip/vsrc/SimSerial.v \
-	$(base_dir)/testchipip/vsrc/SimBlockDevice.v \
+	$(ROCKETCHIP_DIR)/vsrc/TestDriver.v \
+	$(ROCKETCHIP_DIR)/vsrc/AsyncResetReg.v \
+	$(ROCKETCHIP_DIR)/vsrc/plusarg_reader.v \
+	$(testchip_vsrcs)
 
 sim_csrcs = \
-	$(base_dir)/testchipip/csrc/SimSerial.cc \
-	$(base_dir)/testchipip/csrc/SimBlockDevice.cc \
-	$(base_dir)/testchipip/csrc/blkdev.cc \
+	$(testchip_csrcs)
 
 VCS = vcs -full64