Fix some build system problems.

1) Bump testchipip to include forgotten commit
2) Add some support for generating VCS files
3) Fix some makefile deps

Makefrag

@@ -33,7 +33,7 @@ VERILOG_FILE ?=$(build_dir)/$(long_name).top.v
 HARNESS_FILE ?=$(build_dir)/$(long_name).harness.v
 SMEMS_FILE   ?=$(build_dir)/$(long_name).mems.v
 SMEMS_CONF   ?=$(build_dir)/$(long_name).mems.conf
-verilator_dotf ?= $(build_dir)/verilator_files.f
+sim_dotf ?= $(build_dir)/sim_files.f
 
 REPL_SEQ_MEM = --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF)
 
@@ -54,10 +54,10 @@ $(MACROCOMPILER_JAR): $(call lookup_scala_srcs, $(base_dir)/barstools/macros/src
 .PHONY: jars
 jars: $(MACROCOMPILER_JAR) $(TAPEOUT_JAR)
 
-$(verilator_dotf): $(SCALA_SOURCES)
-	cd $(base_dir) && $(SBT) "runMain example.GenerateSimFiles -td $(build_dir)"
+$(sim_dotf): $(SCALA_SOURCES) $(FIRRTL_JAR)
+	cd $(base_dir) && $(SBT) "runMain example.GenerateSimFiles -td $(build_dir) -sim $(sim_name)"
 
-$(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(verilator_dotf)
+$(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf)
 	mkdir -p $(build_dir)
 	cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
 

src/main/scala/example/Simulator.scala

@@ -4,13 +4,28 @@ import java.io.File
 
 case class GenerateSimConfig(
   targetDir: String = ".",
-  dotFName: String = "verilator_files.f",
+  dotFName: String = "sim_files.f",
+  simulator: Simulator = VerilatorSimulator,
 )
 
+sealed trait Simulator
+object VerilatorSimulator extends Simulator
+object VCSSimulator extends Simulator
+
 trait HasGenerateSimConfig {
   val parser = new scopt.OptionParser[GenerateSimConfig]("GenerateSimFiles") {
     head("GenerateSimFiles", "0.1")
 
+    opt[String]("simulator")
+      .abbr("sim")
+      .valueName("<simulator-name>")
+      .action((x, c) => x match {
+        case "verilator" => c.copy(simulator = VerilatorSimulator)
+        case "vcs" => c.copy(simulator = VCSSimulator)
+        case _ => throw new Exception(s"Unrecognized simulator $x")
+      })
+      .text("Name of simulator to generate files for (verilator, vcs)")
+
     opt[String]("target-dir")
       .abbr("td")
       .valueName("<target-directory>")
@@ -61,17 +76,21 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
     out.write(text)
     out.close()
   }
-  val resources = Seq(
-    // TODO(rigge): make conditional on if we are using verilator
-    "/project-template/csrc/emulator.cc",
+  def resources(sim: Simulator): Seq[String] = Seq(
     "/csrc/SimDTM.cc",
     "/csrc/SimJTAG.cc",
     "/csrc/remote_bitbang.h",
     "/csrc/remote_bitbang.cc",
-    "/csrc/verilator.h",
     "/vsrc/EICG_wrapper.v",
-    "/testchipip/bootrom/bootrom.rv64.img",
-  )
+  ) ++ (sim match { // simulator specific files to include
+    case VerilatorSimulator => Seq(
+      "/project-template/csrc/emulator.cc",
+      "/csrc/verilator.h",
+    )
+    case VCSSimulator => Seq(
+      "/vsrc/TestDriver.v",
+    )
+  })
 
   def writeBootrom(): Unit = {
     firrtl.FileUtils.makeDirectory("./bootrom/")
@@ -81,7 +100,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
   def writeFiles(cfg: GenerateSimConfig): Unit = {
     writeBootrom()
     firrtl.FileUtils.makeDirectory(cfg.targetDir)
-    val files = resources.map { writeResource(_, cfg.targetDir) }
+    val files = resources(cfg.simulator).map { writeResource(_, cfg.targetDir) }
     writeDotF(files.map(addOption), cfg)
   }
 

verisim/Makefile

@@ -8,6 +8,8 @@ CFG_PROJECT ?= $(PROJECT)
 TB ?= TestDriver
 TOP ?= ExampleTop
 
+sim_name = verilator
+
 sim = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG)
 sim_debug = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG)-debug
 
@@ -40,11 +42,11 @@ model_header_debug = $(model_dir_debug)/V$(MODEL).h
 model_mk = $(model_dir)/V$(MODEL).mk
 model_mk_debug = $(model_dir_debug)/V$(MODEL).mk
 
-$(model_mk): $(sim_vsrcs) $(verilator_dotf) $(INSTALLED_VERILATOR)
+$(model_mk): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
 	rm -rf $(build_dir)/$(long_name)
 	mkdir -p $(build_dir)/$(long_name)
 	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \
-	-o $(sim) $(sim_vsrcs) -f $(verilator_dotf) -f $(sim_blackboxes) -LDFLAGS "$(LDFLAGS)" \
+	-o $(sim) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_blackboxes) -LDFLAGS "$(LDFLAGS)" \
 	-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)"
 	touch $@
 
@@ -52,11 +54,11 @@ $(sim): $(model_mk)
 	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(MODEL).mk
 
 
-$(model_mk_debug): $(sim_vsrcs) $(verilator_dotf) $(INSTALLED_VERILATOR)
+$(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
 	rm -rf $(build_dir)/$(long_name)
 	mkdir -p $(build_dir)/$(long_name).debug
 	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name).debug --trace \
-	-o $(sim_debug) $(sim_vsrcs) -f $(verilator_dotf) -f $(sim_blackboxes) -LDFLAGS "$(LDFLAGS)" \
+	-o $(sim_debug) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_blackboxes) -LDFLAGS "$(LDFLAGS)" \
 	-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)"
 	touch $@
 

vsim/Makefile

@@ -8,6 +8,8 @@ CFG_PROJECT ?= $(PROJECT)
 TB ?= TestDriver
 TOP ?= ExampleTop
 
+sim_name = vcs
+
 simv = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)
 simv_debug = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)-debug
 
@@ -17,28 +19,25 @@ debug: $(simv_debug)
 
 include $(base_dir)/Makefrag
 
+sim_blackboxes = \
+  $(build_dir)/firrtl_black_box_resource_files.f
+
 rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
 
 sim_vsrcs = \
 	$(VERILOG_FILE) \
 	$(HARNESS_FILE) \
-	$(SMEMS_FILE) \
-	$(rocketchip_vsrc_dir)/TestDriver.v \
-	$(rocketchip_vsrc_dir)/AsyncResetReg.v \
-	$(rocketchip_vsrc_dir)/plusarg_reader.v \
-	$(testchip_vsrcs)
-
-sim_csrcs = \
-	$(testchip_csrcs)
+	$(SMEMS_FILE)
 
 VCS = vcs -full64
 
 VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
 	+rad +v2k +vcs+lic+wait \
 	+vc+list -CC "-I$(VCS_HOME)/include" \
-	-CC "-I$(RISCV)/include -I$(base_dir)/testchipip/csrc" \
+	-CC "-I$(RISCV)/include" \
 	-CC "-std=c++11" \
 	-CC "-Wl,-rpath,$(RISCV)/lib" \
+	-f $(sim_blackboxes) -f $(sim_dotf) \
 	$(RISCV)/lib/libfesvr.so \
 	-sverilog \
 	+incdir+$(generated_dir) \