wu-arch/chipyard
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make sure annotations are generated and carried through to verilog elaboration

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This commit is contained in:
Howard Mao
2018-02-23 11:50:33 -08:00
parent 1dfe9b1c9f
commit 073c16961e
3 changed files with 9 additions and 4 deletions
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10
Makefrag
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@@ -36,9 +36,13 @@ bootrom_img = $(base_dir)/bootrom/bootrom.rv64.img $(base_dir)/bootrom/bootrom.r
CHISEL_ARGS ?=
$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).fir: $(rocketchip_stamp) $(extra_stamps) $(call lookup_scala_srcs,$(base_dir)/src/main/scala) $(bootrom_img)
FIRRTL_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).fir
ANNO_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).anno
VERILOG_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).v
$(FIRRTL_FILE) $(ANNO_FILE): $(rocketchip_stamp) $(extra_stamps) $(call lookup_scala_srcs,$(base_dir)/src/main/scala) $(bootrom_img)
mkdir -p $(build_dir)
cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).v: $(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).fir $(FIRRTL_JAR)
$(FIRRTL) -i $< -o $@ -X verilog
$(VERILOG_FILE): $(FIRRTL_FILE) $(ANNO_FILE) $(FIRRTL_JAR)
$(FIRRTL) -i $(FIRRTL_FILE) -o $(VERILOG_FILE) -X verilog -faf $(ANNO_FILE)

1
src/main/scala/example/TestHarness.scala
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@@ -22,4 +22,5 @@ class TestHarness(implicit val p: Parameters) extends Module {
object Generator extends GeneratorApp {
generateFirrtl
generateAnno
}

2
testchipip

Submodule testchipip updated: 3cd6ece873...693698bb4b