bump rocket-chip to March commit

build.sbt

@@ -4,4 +4,4 @@ version := "1.0"
 
 name := "testchip-example"
 
-scalaVersion := "2.11.7"
+scalaVersion := "2.11.12"

src/main/scala/example/Configs.scala

@@ -2,7 +2,7 @@ package example
 
 import chisel3._
 import freechips.rocketchip.config.{Parameters, Config}
-import freechips.rocketchip.coreplex.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32}
+import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32}
 import freechips.rocketchip.diplomacy.{LazyModule, ValName}
 import freechips.rocketchip.devices.tilelink.BootROMParams
 import freechips.rocketchip.tile.XLen

src/main/scala/example/PWM.scala

@@ -2,7 +2,7 @@ package example
 
 import chisel3._
 import chisel3.util._
-import freechips.rocketchip.coreplex.HasPeripheryBus
+import freechips.rocketchip.subsystem.BaseSubsystem
 import freechips.rocketchip.config.{Parameters, Field}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper.{HasRegMap, RegField}
@@ -71,15 +71,16 @@ class PWMTL(c: PWMParams)(implicit p: Parameters)
       new TLRegBundle(c, _) with PWMTLBundle)(
       new TLRegModule(c, _, _) with PWMTLModule)
 
-trait HasPeripheryPWM extends HasPeripheryBus {
+trait HasPeripheryPWM { this: BaseSubsystem =>
   implicit val p: Parameters
 
   private val address = 0x2000
+  private val portName = "pwm"
 
   val pwm = LazyModule(new PWMTL(
     PWMParams(address, pbus.beatBytes))(p))
 
-  pwm.node := pbus.toVariableWidthSlaves
+  pbus.toVariableWidthSlave(Some(portName)) { pwm.node }
 }
 
 trait HasPeripheryPWMModuleImp extends LazyModuleImp {

src/main/scala/example/Top.scala

@@ -1,13 +1,13 @@
 package example
 
 import chisel3._
-import freechips.rocketchip.coreplex._
+import freechips.rocketchip.subsystem._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.util.DontTouch
 import testchipip._
 
-class ExampleTop(implicit p: Parameters) extends RocketCoreplex
+class ExampleTop(implicit p: Parameters) extends RocketSubsystem
     with HasMasterAXI4MemPort
     with HasPeripheryBootROM
     with HasSystemErrorSlave
@@ -17,7 +17,7 @@ class ExampleTop(implicit p: Parameters) extends RocketCoreplex
   override lazy val module = new ExampleTopModule(this)
 }
 
-class ExampleTopModule[+L <: ExampleTop](l: L) extends RocketCoreplexModule(l)
+class ExampleTopModule[+L <: ExampleTop](l: L) extends RocketSubsystemModuleImp(l)
     with HasRTCModuleImp
     with HasMasterAXI4MemPortModuleImp
     with HasPeripheryBootROMModuleImp