update verilator so that plusarg_reader works

src/main/scala/example/Configs.scala

@@ -50,7 +50,6 @@ class WithSimNetwork extends Config((site, here, up) => {
 })
 
 class BaseExampleConfig extends Config(
-  new WithoutTLMonitors ++
   new WithSerialAdapter ++
   new freechips.rocketchip.chip.DefaultConfig)
 

verisim/Makefile

@@ -69,4 +69,4 @@ $(sim_debug): $(model_mk_debug) $(sim_csrcs)
 	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(MODEL).mk
 
 clean:
-	rm -rf generated-src
+	rm -rf generated-src ./simulator-*

verisim/Makefrag-verilator

@@ -1,5 +1,5 @@
 # Build and install our own Verilator, to work around versionining issues.
-VERILATOR_VERSION=3.884
+VERILATOR_VERSION=3.904
 VERILATOR_SRCDIR=verilator/src/verilator-$(VERILATOR_VERSION)
 INSTALLED_VERILATOR=$(abspath verilator/install/bin/verilator)
 $(INSTALLED_VERILATOR): $(VERILATOR_SRCDIR)/bin/verilator