bump boom/firrtl | support building boom | update genfiles in simulator to make rv32 bootrom | misc cleanup

sims/verisim/Makefile

@@ -89,5 +89,5 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
 # general cleanup rule
 #########################################################################################
 .PHONY: clean
-clean: clean-scala
+clean:
 	rm -rf $(build_dir) $(sim_prefix)-*

sims/vsim/Makefile

@@ -93,5 +93,5 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
 # general cleanup rule
 #########################################################################################
 .PHONY: clean
-clean: clean-scala
+clean:
 	rm -rf $(build_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h

src/main/scala/example/Simulator.scala

@@ -101,6 +101,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
   def writeBootrom(): Unit = {
     firrtl.FileUtils.makeDirectory("./bootrom/")
     writeResource("/testchipip/bootrom/bootrom.rv64.img", "./bootrom/")
+    writeResource("/testchipip/bootrom/bootrom.rv32.img", "./bootrom/")
   }
 
   def writeFiles(cfg: GenerateSimConfig): Unit = {