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  • e40b7f0b8b Support receiving trace filename from VPI for loggers Hansung Kim 2023-05-28 22:15:32 -07:00
  • af01e39b5a Revamp dataflow between uncoalescer and inflight table Hansung Kim 2023-05-27 13:59:25 -07:00
  • aada78da33 Fix writing to inflight table when valid not fire Hansung Kim 2023-05-27 13:02:00 -07:00
  • da3cfa9bd9 Minor doc Hansung Kim 2023-05-21 11:21:51 -07:00
  • 5491491a6b Fix newSrcId truncation in InFlightTableEntry Hansung Kim 2023-05-21 02:50:04 -07:00
  • 1d6d35233f Move multi-beat warning to inside param class Hansung Kim 2023-05-20 00:44:27 -07:00
  • 7c7752a5a2 Disable uncoalescer unit test temporarily Hansung Kim 2023-05-20 00:23:18 -07:00
  • 1243fd75a2 Fix old param name in XBarUnitTest Hansung Kim 2023-05-20 00:22:40 -07:00
  • 2a0fd24d17 Make SourceGenerator do CAM search for lowest-index free slot Hansung Kim 2023-05-19 23:52:35 -07:00
  • 9ecace676c Add useful error msg Vamber Yang 2023-05-19 17:47:40 -07:00
  • 0d96d81968 Make numOldSrcIds and numNewSrcIds parameters of SoC Vamber Yang 2023-05-19 17:47:18 -07:00
  • ab3ce82aff Fixed MemTracerDriverImpr to generate the last request when SimMemTrace outputs finished signal Vamber Yang 2023-05-19 05:03:13 -07:00
  • d88a734aee Fixed MemTracerDriverImp to only terminate when all outstanding reqs are reclaimed This is for slightly more accurate perf numbers. Vamber Yang 2023-05-19 03:16:52 -07:00
  • d234b8c09a Add RTL for Coalescer Priority XBar and relevant keys&configs for SoC Integration Vamber Yang 2023-05-16 20:22:49 -07:00
  • ebf81babc1 Modified WithCoalescer to dynamically configure databusWidth and MaxCoalSize according to underlying SoC setting, This makes running perf numbers easier Vamber Yang 2023-05-16 05:57:35 -07:00
  • 148e2550fa Propagate sourceGen backpressure into MultiCoalescer Hansung Kim 2023-05-16 00:24:26 -07:00
  • 3549f62e55 Fix sourcegen update logic for coalReq Hansung Kim 2023-05-15 23:13:45 -07:00
  • 869c6c9f9c Fix backpressure for coalReq not being respected Hansung Kim 2023-05-15 22:22:52 -07:00
  • 7b5ea31cdf Fix wrong uncoalescer valid Hansung Kim 2023-05-15 21:16:14 -07:00
  • d8cd2eae75 Fix size truncation in CoalescedRequest Hansung Kim 2023-05-15 20:42:59 -07:00
  • 6660775956 Synchronize requests across lanes from MemTraceDriver Hansung Kim 2023-05-14 22:02:23 -07:00
  • 64de77d350 Enable memtrace logger in SoC config Hansung Kim 2023-05-14 19:21:08 -07:00
  • e7b3455127 Disable coverage policy for easier eval Hansung Kim 2023-05-14 19:20:36 -07:00
  • 9fd507fe46 Connect to response queue internally in Uncoalescer Hansung Kim 2023-05-14 16:26:39 -07:00
  • d8e9dab329 Separate sourcegen for coalesced req for clearer dataflow Hansung Kim 2023-05-14 16:09:09 -07:00
  • e02e4ca500 Handle backpressure from CoalescerNode Hansung Kim 2023-05-12 01:05:23 -07:00
  • 7e6ebb9e35 Create SoC-integrated Config for Coalescer Hansung Kim 2023-05-12 01:01:21 -07:00
  • 80ffc6cc73 write striping across banks Richard Yan 2023-05-12 00:31:28 -07:00
  • 4e4b993287 Merge branch 'graphics' of https://github.com/hansungk/rocket-chip into graphics Richard Yan 2023-05-11 21:50:42 -07:00
  • 9b7080a852 Delete old inflight table unittest Hansung Kim 2023-05-11 18:50:47 -07:00
  • 226e1d2d84 Fix uncoalescer unittest even more Hansung Kim 2023-05-11 18:30:15 -07:00
  • b95b59cce0 Fix uncoalescer unittest Hansung Kim 2023-05-11 18:30:15 -07:00
  • df68bfec84 Remove module dependency for uncoalescer instantiation Hansung Kim 2023-05-11 18:20:19 -07:00
  • f0a7fd852a WIP bank striping Richard Yan 2023-05-11 18:12:25 -07:00
  • 0df3192882 Revamp uncoalescer IO Hansung Kim 2023-05-11 17:31:51 -07:00
  • 772deda9c2 Fix ChiselEnum experimental warning Hansung Kim 2023-05-11 16:20:01 -07:00
  • 0c8909cb43 scalafmt Hansung Kim 2023-05-11 16:11:39 -07:00
  • 7fa6be4a8b Use case class for noncoal/coal bundles Hansung Kim 2023-05-11 15:56:30 -07:00
  • 406f90b633 De-duplicate equivalent Request bundles using NonCoal/Coal variants Hansung Kim 2023-05-11 15:50:58 -07:00
  • 5fed3ef823 Generalize Req/RespQueueEntry into Response/Request bundle Hansung Kim 2023-05-11 15:42:23 -07:00
  • 300eff4f9a Fix misleading maxSize param in Req/RespQueueEntry Hansung Kim 2023-05-10 19:55:01 -07:00
  • 4f31cad513 Merge remote-tracking branch 'origin/graphics' into local-dev-branch Vamber Yang 2023-05-10 19:02:16 -07:00
  • 1633371f6f Coalescer XBar, a design overhaul from CoalArbiter, the best way to implement the 'arbiter' functionality is to implement as a TLXbar with different arbitration policy (RR + PO) Vamber Yang 2023-05-10 18:59:36 -07:00
  • b48ab70e67 Fix assertion falsely firing on invalid Hansung Kim 2023-05-10 00:26:25 -07:00
  • 19d378dc3a Fix sourceGen unasserted firrtl error Hansung Kim 2023-05-10 00:13:04 -07:00
  • 6032d79ead Implement proper source gen Hansung Kim 2023-05-09 23:46:11 -07:00
  • 1886aefcc1 Parameterize tracefile has_source from Config Hansung Kim 2023-05-09 22:22:27 -07:00
  • 89398cdc3d Fix CanHaveMemtraceCore not setting numLane Hansung Kim 2023-05-09 19:02:03 -07:00
  • 2ade624343 Fix backpressure handling in MemTraceDriver when attached to SoC Hansung Kim 2023-05-09 17:52:27 -07:00
  • f52492c56b Create separate config for memtrace core Hansung Kim 2023-05-09 13:07:38 -07:00
  • 7bd9fd43f8 Merge branch 'graphics' of https://github.com/hansungk/rocket-chip into graphics Richard Yan 2023-05-09 09:37:59 -07:00
  • bce2c6230f more test fixes Richard Yan 2023-05-09 09:36:29 -07:00
  • 9059d1e436 Misc doc Hansung Kim 2023-05-08 20:35:40 -07:00
  • fd0d09691b Create separate Configs for synthesizable dummy testbenches Hansung Kim 2023-05-08 17:51:24 -07:00
  • f6be54a122 Set up proper Config system for numLanes Hansung Kim 2023-05-08 17:32:31 -07:00
  • 25c0b6cfa5 CoalArbiter RTL written, verification WIP, merged changes from graphics Vamber Yang 2023-05-08 16:57:26 -07:00
  • 9c2a55ae79 CoalArbiter RTL implementation first draft, verification WIP Vamber Yang 2023-05-08 16:52:45 -07:00
  • 3fae0b2c7a Use priority encoder for chooseLeaderIdx Hansung Kim 2023-05-08 15:18:45 -07:00
  • 2d4e28e862 Use WithoutTLMonitors to slightly speed up chiseltests Hansung Kim 2023-05-08 14:38:15 -07:00
  • 54a3e3cf72 Initiate memtrace DPI only when trace_read_ready Hansung Kim 2023-05-08 14:34:52 -07:00
  • 2e219ea15a Connect CoalShiftQueue enq.ready to upstream TL.ready Hansung Kim 2023-05-08 14:27:54 -07:00
  • 8cdbc81bdd Only write in MemTraceLogger when TL fire Hansung Kim 2023-05-08 14:26:05 -07:00
  • 6755cb3eec Lax traceReadCycle advancing logic Hansung Kim 2023-05-08 00:49:30 -07:00
  • 6b97b77572 Revert SimMemTrace.v to use posedge clock Hansung Kim 2023-05-08 00:14:48 -07:00
  • 99d1e45a49 CoalArbiter RTL outgoing side implementation Vamber Yang 2023-05-08 00:05:16 -07:00
  • f7df5045d4 Respect downstream TL A ready in MemTraceDriver Hansung Kim 2023-05-07 23:55:54 -07:00
  • ba600db7e4 Backport SimMemTrace fix Hansung Kim 2023-05-07 23:54:49 -07:00
  • 737a760fcd Enable coverage tests for chiseltest Hansung Kim 2023-05-07 22:58:01 -07:00
  • 15889d7667 Take filename from Configs for easier trace testing Hansung Kim 2023-05-07 19:09:25 -07:00
  • c75eaaf727 Backport SimMemTrace Hansung Kim 2023-05-07 16:13:28 -07:00
  • a6dbfc3901 Fix config for unittest Hansung Kim 2023-05-07 16:12:59 -07:00
  • 5e073f2dec Doc update Hansung Kim 2023-05-07 12:37:33 -07:00
  • d2e56be157 update unit tests for new timing behavior & config Richard Yan 2023-05-07 14:35:53 -07:00
  • 262a20c992 Merge branch 'graphics' of https://github.com/hansungk/rocket-chip into graphics Richard Yan 2023-05-07 02:34:11 -07:00
  • 86e7d3d60d numerous coalescer bug fixes + working unit test Richard Yan 2023-05-07 02:31:28 -07:00
  • 2d4cd542c1 Backport SimMemTrace: non-chronological trace error Hansung Kim 2023-05-06 23:21:08 -07:00
  • e64cb7a282 Backport SimMemTrace: enable parsing source, report errors Hansung Kim 2023-05-06 23:13:45 -07:00
  • afd8a0910a Rename arbiter config and IO Hansung Kim 2023-05-06 18:36:46 -07:00
  • caa5ebf943 Reformat MemTraceReader Hansung Kim 2023-05-06 01:47:33 -07:00
  • c783f147f9 Merge branch 'graphics' of https://github.com/hansungk/rocket-chip into graphics Richard Yan 2023-05-05 23:02:28 -07:00
  • 457b67a8d4 coalReqT source width bug fix Richard Yan 2023-05-05 23:02:25 -07:00
  • 124e974969 Merge remote-tracking branch 'origin/graphics' into local-dev-branch Vamber Yang 2023-05-05 19:00:21 -07:00
  • 3dad961082 define top level IO bundle for CoalArbiter Vamber Yang 2023-05-05 19:00:01 -07:00
  • 4ebcfbb9eb Revert deq.valid; force-set io.coalesceable instead for coal.enable Hansung Kim 2023-05-05 15:51:59 -07:00
  • 42b03edbf7 Update import path to cde to reflect upstream changes Hansung Kim 2023-05-05 14:50:25 -07:00
  • bb6105a0c7 Add missing reset to CoalShiftQueue Hansung Kim 2023-05-04 17:26:12 -07:00
  • aa0ce2998e Respect io.coalescable for deq.valid in CoalShiftQueue Hansung Kim 2023-05-04 16:40:20 -07:00
  • 1fa2e36740 Add global enable to coalescer config Hansung Kim 2023-05-04 16:38:38 -07:00
  • eb802a2aaa Fix srcId config mismatch with MemTraceDriver Hansung Kim 2023-05-04 15:40:46 -07:00
  • a1cdf10b20 Revert to non-synthesis TB; wip config compile error fix Hansung Kim 2023-05-04 15:33:44 -07:00
  • 888e4f091e Leftover synthesis dummy changes Hansung Kim 2023-05-04 15:23:44 -07:00
  • d4c2173f6e Merge branch 'graphics' of https://github.com/hansungk/rocket-chip into graphics Richard Yan 2023-05-03 17:59:20 -07:00
  • ebd6c54d67 tl graph changes, coalescer bug fixes & coalescer unit test Richard Yan 2023-05-03 17:58:25 -07:00
  • 84cc0334bb Get latest change from graphics before pushing Merge remote-tracking branch 'origin/graphics' into local-dev-branch Vamber Yang 2023-05-02 22:07:12 -07:00
  • 8ccaf3864d Support for more realistic MemTracer step2 (DONE), make Verilog Blackbox DPI output data immediately and make .cc file maintain pointer when downstream is not ready Vamber Yang 2023-05-02 22:06:16 -07:00
  • 736a8d4e98 Merge branch 'graphics' of https://github.com/hansungk/rocket-chip into graphics Richard Yan 2023-05-02 17:40:08 -07:00
  • 459c14bb62 add testing infrastructure for coalescing unit Richard Yan 2023-05-02 17:38:49 -07:00
  • be0fcbd23b Support for more realistic MemTracer step 1, allow Chisel MemTracer to input read_cycle to Verilog blackbox Vamber Yang 2023-05-02 14:01:19 -07:00
  • b9953e43ca TL helper methods for entry types Richard Yan 2023-05-02 01:39:27 -07:00
  • 997b421c42 active byte lane implementation for multi coalescer & add one shift queue test Richard Yan 2023-05-02 00:07:45 -07:00