Merge branch 'graphics' of https://github.com/hansungk/rocket-chip into graphics
This commit is contained in:
Richard Yan
File diff suppressed because it is too large
Load Diff
@@ -180,12 +180,12 @@ class DummyCoalescingUnitTBImp(outer: DummyCoalescingUnitTB) extends LazyModuleI
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)
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val reqQueueEnqReady = peekIn(0).asInstanceOf[Seq[Bool]].map(x => IO(x.cloneType))
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val reqQueueEnqBits = peekIn(1).asInstanceOf[Seq[ReqQueueEntry]].map(x => IO(x.cloneType))
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val reqQueueEnqBits = peekIn(1).asInstanceOf[Seq[Request]].map(x => IO(x.cloneType))
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val reqQueueEnqValid = peekIn(2).asInstanceOf[Seq[Bool]].map(x => IO(x.cloneType))
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val reqQueueDeqBits = peekIn(3).asInstanceOf[Seq[ReqQueueEntry]].map(x => IO(Output(x.cloneType)))
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val reqQueueDeqBits = peekIn(3).asInstanceOf[Seq[Request]].map(x => IO(Output(x.cloneType)))
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val reqQueueDeqValid = peekIn(4).asInstanceOf[Seq[Bool]].map(x => IO(Output(x.cloneType)))
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val coalReqReady = IO(Output(peekIn(5).asInstanceOf[Bool].cloneType))
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val coalReqBits = IO(Output(peekIn(6).asInstanceOf[ReqQueueEntry].cloneType))
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val coalReqBits = IO(Output(peekIn(6).asInstanceOf[Request].cloneType))
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val coalReqValid = IO(Output(peekIn(7).asInstanceOf[Bool].cloneType))
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val coalInvalidate = IO(Output(peekIn(8).asInstanceOf[Valid[Vec[UInt]]].cloneType))
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@@ -759,67 +759,70 @@ class CoalShiftQueueTest extends AnyFlatSpec with ChiselScalatestTester {
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}*/
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}
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object uncoalescerTestConfig extends CoalescerConfig(
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enable = true,
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numLanes = 4,
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queueDepth = 2,
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waitTimeout = 8,
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addressWidth = 24,
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dataBusWidth = 5,
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// watermark = 2,
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wordSizeInBytes = 4,
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numOldSrcIds = 16,
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numNewSrcIds = 4,
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respQueueDepth = 4,
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coalLogSizes = Seq(4),
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sizeEnum = DefaultInFlightTableSizeEnum,
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numCoalReqs = 1,
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numArbiterOutputPorts = 4,
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bankStrideInBytes = 64,
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)
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class UncoalescerUnitTest extends AnyFlatSpec with ChiselScalatestTester {
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behavior of "uncoalescer"
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val numLanes = 4
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val numPerLaneReqs = 2
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val sourceWidth = 2
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val sizeWidth = 2
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// 16B coalescing size
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val coalDataWidth = 128
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val numInflightCoalRequests = 4
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object uncoalescerTestConfig extends CoalescerConfig(
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enable = true,
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numLanes = 4,
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queueDepth = 2,
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waitTimeout = 8,
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addressWidth = 24,
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dataBusWidth = 4, // 128 bit data bus
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wordSizeInBytes = 4,
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numOldSrcIds = 16,
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numNewSrcIds = 4,
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respQueueDepth = 4,
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coalLogSizes = Seq(4),
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sizeEnum = DefaultInFlightTableSizeEnum,
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numCoalReqs = 1,
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numArbiterOutputPorts = 4,
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bankStrideInBytes = 64,
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)
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val config = uncoalescerTestConfig
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val nonCoalReqT = new NonCoalescedRequest(config)
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val coalReqT = new CoalescedRequest(config)
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it should "work in general case" in {
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test(new Uncoalescer(uncoalescerTestConfig))
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test(new Uncoalescer(config, nonCoalReqT, coalReqT))
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// vcs helps with simulation time, but sometimes errors with
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// "mutation occurred during iteration" java error
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// .withAnnotations(Seq(VcsBackendAnnotation))
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{ c =>
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// 4 lanes, queue depth 2
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c.io.windowElts(0)(0).op.poke(0.U)
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c.io.windowElts(0)(0).source.poke(1.U)
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c.io.windowElts(0)(0).address.poke(0x4.U)
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c.io.windowElts(0)(0).size.poke(2.U)
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c.io.windowElts(0)(1).op.poke(0.U)
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c.io.windowElts(0)(1).source.poke(2.U)
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c.io.windowElts(0)(1).address.poke(0x4.U) // two reqs from one lane
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c.io.windowElts(0)(1).size.poke(2.U)
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c.io.windowElts(2)(0).op.poke(0.U)
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c.io.windowElts(2)(0).source.poke(2.U)
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c.io.windowElts(2)(0).address.poke(0x8.U)
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c.io.windowElts(2)(0).size.poke(2.U)
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c.io.windowElts(2)(1).op.poke(0.U)
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c.io.windowElts(2)(1).source.poke(2.U)
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c.io.windowElts(2)(1).address.poke(0xc.U)
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c.io.windowElts(2)(1).size.poke(2.U)
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// indicate lane 0 and 2 are used for coalescing
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c.io.invalidate.valid.poke(true.B)
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c.io.invalidate.bits(0).poke(0x3.U) // 2'b11 for depth=2
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c.io.invalidate.bits(1).poke(0x0.U)
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c.io.invalidate.bits(2).poke(0x3.U)
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c.io.invalidate.bits(3).poke(0x0.U)
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val sourceId = 0.U
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val four = c.io.newEntry.sizeEnumT.FOUR
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c.io.coalReqValid.poke(true.B)
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c.io.newEntry.source.poke(sourceId)
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c.io.newEntry.lanes(0).reqs(0).valid.poke(true.B)
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c.io.newEntry.lanes(0).reqs(0).source.poke(1.U)
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c.io.newEntry.lanes(0).reqs(0).offset.poke(1.U)
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c.io.newEntry.lanes(0).reqs(0).sizeEnum.poke(four)
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c.io.newEntry.lanes(0).reqs(1).valid.poke(true.B)
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c.io.newEntry.lanes(0).reqs(1).source.poke(2.U)
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c.io.newEntry.lanes(0).reqs(1).offset.poke(1.U) // same offset to different lanes
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c.io.newEntry.lanes(0).reqs(1).sizeEnum.poke(four)
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c.io.newEntry.lanes(1).reqs(0).valid.poke(false.B)
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c.io.newEntry.lanes(2).reqs(0).valid.poke(true.B)
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c.io.newEntry.lanes(2).reqs(0).source.poke(2.U)
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c.io.newEntry.lanes(2).reqs(0).offset.poke(2.U)
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c.io.newEntry.lanes(2).reqs(0).sizeEnum.poke(four)
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c.io.newEntry.lanes(2).reqs(1).valid.poke(true.B)
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c.io.newEntry.lanes(2).reqs(1).source.poke(2.U)
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c.io.newEntry.lanes(2).reqs(1).offset.poke(3.U)
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c.io.newEntry.lanes(2).reqs(1).sizeEnum.poke(four)
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c.io.newEntry.lanes(3).reqs(0).valid.poke(false.B)
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c.io.coalReq.valid.poke(true.B)
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c.io.coalReq.bits.source.poke(sourceId)
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c.io.coalReq.ready.expect(true.B)
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c.clock.step()
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c.io.coalReqValid.poke(false.B)
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c.io.coalReq.valid.poke(false.B)
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c.io.invalidate.valid.poke(false.B)
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c.clock.step()
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@@ -848,37 +851,42 @@ class UncoalescerUnitTest extends AnyFlatSpec with ChiselScalatestTester {
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}
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it should "uncoalesce when coalesced to the same word offset" in {
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test(new Uncoalescer(uncoalescerTestConfig))
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test(new Uncoalescer(config, nonCoalReqT, coalReqT))
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// .withAnnotations(Seq(VcsBackendAnnotation))
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{ c =>
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// 4 lanes, queue depth 2
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c.io.windowElts(0)(0).op.poke(0.U)
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c.io.windowElts(0)(0).source.poke(0.U)
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c.io.windowElts(0)(0).address.poke(0x4.U)
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c.io.windowElts(0)(0).size.poke(2.U)
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c.io.windowElts(1)(0).op.poke(0.U)
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c.io.windowElts(1)(0).source.poke(1.U)
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c.io.windowElts(1)(0).address.poke(0x4.U) // two reqs from one lane
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c.io.windowElts(1)(0).size.poke(2.U)
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c.io.windowElts(2)(0).op.poke(0.U)
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c.io.windowElts(2)(0).source.poke(2.U)
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c.io.windowElts(2)(0).address.poke(0x4.U)
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c.io.windowElts(2)(0).size.poke(2.U)
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c.io.windowElts(3)(0).op.poke(0.U)
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c.io.windowElts(3)(0).source.poke(3.U)
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c.io.windowElts(3)(0).address.poke(0x4.U)
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c.io.windowElts(3)(0).size.poke(2.U)
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// indicate lanes used for coalescing
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c.io.invalidate.valid.poke(true.B)
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c.io.invalidate.bits(0).poke(0x1.U) // 2'b01 for enabling head
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c.io.invalidate.bits(1).poke(0x1.U)
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c.io.invalidate.bits(2).poke(0x1.U)
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c.io.invalidate.bits(3).poke(0x1.U)
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val sourceId = 0.U
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val four = c.io.newEntry.sizeEnumT.FOUR
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c.io.coalReqValid.poke(true.B)
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c.io.newEntry.source.poke(sourceId)
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c.io.newEntry.lanes(0).reqs(0).valid.poke(true.B)
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c.io.newEntry.lanes(0).reqs(0).source.poke(0.U)
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c.io.newEntry.lanes(0).reqs(0).offset.poke(1.U)
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c.io.newEntry.lanes(0).reqs(0).sizeEnum.poke(four)
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c.io.newEntry.lanes(0).reqs(1).valid.poke(false.B)
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c.io.newEntry.lanes(1).reqs(0).valid.poke(true.B)
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c.io.newEntry.lanes(1).reqs(0).source.poke(1.U)
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c.io.newEntry.lanes(1).reqs(0).offset.poke(1.U)
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c.io.newEntry.lanes(1).reqs(0).sizeEnum.poke(four)
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c.io.newEntry.lanes(1).reqs(1).valid.poke(false.B)
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c.io.newEntry.lanes(2).reqs(0).valid.poke(true.B)
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c.io.newEntry.lanes(2).reqs(0).source.poke(2.U)
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c.io.newEntry.lanes(2).reqs(0).offset.poke(1.U)
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c.io.newEntry.lanes(2).reqs(0).sizeEnum.poke(four)
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c.io.newEntry.lanes(2).reqs(1).valid.poke(false.B)
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c.io.newEntry.lanes(3).reqs(0).valid.poke(true.B)
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c.io.newEntry.lanes(3).reqs(0).source.poke(3.U)
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c.io.newEntry.lanes(3).reqs(0).offset.poke(1.U)
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c.io.newEntry.lanes(3).reqs(0).sizeEnum.poke(four)
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c.io.newEntry.lanes(3).reqs(1).valid.poke(false.B)
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c.io.coalReq.valid.poke(true.B)
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c.io.coalReq.bits.source.poke(sourceId)
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c.io.coalReq.ready.expect(true.B)
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c.clock.step()
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c.io.coalReqValid.poke(false.B)
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c.io.coalReq.valid.poke(false.B)
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c.io.invalidate.valid.poke(false.B)
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c.clock.step()
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@@ -908,138 +916,3 @@ class UncoalescerUnitTest extends AnyFlatSpec with ChiselScalatestTester {
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}
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}
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}
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class CoalInflightTableUnitTest extends AnyFlatSpec with ChiselScalatestTester {
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behavior of "inflight coalesced request table"
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val numLanes = 4
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val numPerLaneReqs = 2
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val sourceWidth = 2
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val entries = 4
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val offsetBits = 4
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val sizeBits = 2
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val inflightCoalReqTableEntry =
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new InflightCoalReqTableEntry(
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numLanes,
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numPerLaneReqs,
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sourceWidth,
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offsetBits,
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testConfig.sizeEnum
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)
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// it should "stop enqueueing when full" in {
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// test(new InflightCoalReqTable(numLanes, sourceWidth, entries)) { c =>
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// // fill up the table
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// for (i <- 0 until entries) {
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// val sourceId = i
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// c.io.enq.ready.expect(true.B)
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// c.io.enq.valid.poke(true.B)
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// c.io.enq.bits.fromLane.poke(0.U)
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// c.io.enq.bits.respSourceId.poke(sourceId.U)
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// c.io.enq.bits.reqSourceIds.foreach { id => id.poke(0.U) }
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// c.io.lookup.ready.poke(false.B)
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// c.clock.step()
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// }
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// // now cannot enqueue any more
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// c.io.enq.ready.expect(false.B)
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// c.io.enq.valid.poke(true.B)
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// c.io.enq.bits.fromLane.poke(0.U)
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// c.io.enq.bits.respSourceId.poke(0.U)
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// c.io.enq.bits.reqSourceIds.foreach { id => id.poke(0.U) }
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// c.clock.step()
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// c.io.enq.ready.expect(false.B)
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// // try to lookup all existing entries
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// for (i <- 0 until entries) {
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// val sourceId = i
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// c.io.enq.valid.poke(false.B)
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// c.io.lookup.ready.poke(true.B)
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// c.io.lookupSourceId.poke(sourceId)
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// c.io.lookup.valid.expect(true.B)
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// c.io.lookup.bits.expect(sourceId)
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// c.clock.step()
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// }
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// // now the table should be empty
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// for (i <- 0 until entries) {
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// val sourceId = i
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// c.io.enq.valid.poke(false.B)
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// c.io.lookup.ready.poke(true.B)
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// c.io.lookupSourceId.poke(sourceId)
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// c.io.lookup.valid.expect(false.B)
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// c.clock.step()
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// }
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// }
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// }
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// it should "lookup matching entry" in {
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// test(new InflightCoalReqTable(numLanes, sourceWidth, entries))
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// .withAnnotations(Seq(WriteVcdAnnotation)) { c =>
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// c.reset.poke(true.B)
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// c.clock.step(10)
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// c.reset.poke(false.B)
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// // enqueue one entry to not match at 0th index
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// c.io.enq.ready.expect(true.B)
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// c.io.enq.valid.poke(true.B)
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// c.io.enq.bits.fromLane.poke(0.U)
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// c.io.enq.bits.respSourceId.poke(0.U)
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// c.io.enq.bits.reqSourceIds.foreach { id => id.poke(0.U) }
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// c.clock.step()
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// val targetSourceId = 1.U
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// c.io.enq.ready.expect(true.B)
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// c.io.enq.valid.poke(true.B)
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// c.io.enq.bits.fromLane.poke(0.U)
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// c.io.enq.bits.respSourceId.poke(targetSourceId)
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// c.io.enq.bits.reqSourceIds.foreach { id => id.poke(0.U) }
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// c.clock.step()
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// c.io.lookup.ready.poke(true.B)
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// c.io.lookupSourceId.poke(targetSourceId)
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// c.io.lookup.valid.expect(true.B)
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// c.io.lookup.bits.expect(targetSourceId)
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// c.clock.step()
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// // test if matching entry dequeues after 1 cycle
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// c.io.lookup.ready.poke(true.B)
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// c.io.lookupSourceId.poke(targetSourceId)
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// c.io.lookup.valid.expect(false.B)
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// }
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// }
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// it should "handle lookup and enqueue at the same time" in {
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// test(new InflightCoalReqTable(numLanes, sourceWidth, entries)) { c =>
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// // fill up the table
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// val targetSourceId = 1.U
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// c.io.enq.ready.expect(true.B)
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// c.io.enq.valid.poke(true.B)
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// c.io.enq.bits.fromLane.poke(0.U)
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// c.io.enq.bits.respSourceId.poke(0.U)
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// c.io.enq.bits.reqSourceIds.foreach { id => id.poke(0.U) }
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// c.clock.step()
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// c.io.enq.ready.expect(true.B)
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// c.io.enq.valid.poke(true.B)
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// c.io.enq.bits.fromLane.poke(0.U)
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// c.io.enq.bits.respSourceId.poke(targetSourceId)
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// c.io.enq.bits.reqSourceIds.foreach { id => id.poke(0.U) }
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// c.clock.step()
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// // do both enqueue and lookup at the same cycle
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// val enqSourceId = 2.U
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// c.io.enq.ready.expect(true.B)
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// c.io.enq.valid.poke(true.B)
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// c.io.enq.bits.fromLane.poke(0.U)
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// c.io.enq.bits.respSourceId.poke(enqSourceId)
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// c.io.enq.bits.reqSourceIds.foreach { id => id.poke(0.U) }
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// c.io.lookup.ready.poke(true.B)
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// c.io.lookupSourceId.poke(targetSourceId)
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// c.clock.step()
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// }
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// }
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}
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Reference in New Issue
Block a user