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Update import path to cde to reflect upstream changes

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This commit is contained in:
Hansung Kim
2023-05-05 14:50:25 -07:00
parent bb6105a0c7
commit 42b03edbf7
3 changed files with 3 additions and 4 deletions
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2
src/main/scala/tilelink/Coalescing.scala
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@@ -5,7 +5,7 @@ package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.ChiselEnum
import freechips.rocketchip.config.Parameters
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
// import freechips.rocketchip.devices.tilelink.TLTestRAM
import freechips.rocketchip.util.MultiPortQueue

3
src/main/scala/tilelink/TracerSystemMem.scala
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@@ -3,10 +3,9 @@ package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes}
import freechips.rocketchip.config.{Parameters, Field, Config}
import org.chipsalliance.cde.config.{Parameters, Field, Config}
// class class, consumed by WithGPUTacer config and GPUTracerKey

2
src/test/scala/coalescing/CoalescingUnitTest.scala
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@@ -6,7 +6,7 @@ import org.scalatest.flatspec.AnyFlatSpec
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util.MultiPortQueue
import freechips.rocketchip.diplomacy._
import chipsalliance.rocketchip.config.Parameters
import org.chipsalliance.cde.config.Parameters
import chisel3.util.{DecoupledIO, Valid}
import chisel3.util.experimental.BoringUtils