d51ce4cfa8
Reformat
Hansung Kim
2023-11-10 14:46:33 -08:00
17a39a369f
Cleanup conditional L1 instantiation
Hansung Kim
2023-11-10 14:42:33 -08:00
a0c15b2cc3
Use separate {imem,dmem}SourceWidth to fix deadlock
Hansung Kim
2023-11-08 20:20:17 -08:00
2f205be702
Update docs
Hansung Kim
2023-11-08 14:02:25 -08:00
571d33a5de
Remove unused MSB offset code from get getCoalescedDataChunk
Hansung Kim
2023-11-06 13:40:25 -08:00
61aad0315c
L1 FatBank Integration, multi-bank working with 4 dcache banks, 1 icache bank
Vamber Yang
2023-11-06 20:51:54 -08:00
e958ede277
multi-bank working when nBanks=2, encountered a putPartial error, need to pull latest change
Vamber Yang
2023-11-06 20:51:23 -08:00
be5134cd8a
L1 fatbank works with 2^5 source bits in SourceGen, failed with < 2^4 source bits in SourceGen
Vamber Yang
2023-11-01 23:48:24 -07:00
d2bfc31592
Fix store opcode assertion in AOpcodeIsStore
Hansung Kim
2023-10-31 23:06:35 -07:00
75adb1dc66
Intergation of L1 Fatbank
Vamber Yang
2023-10-31 16:14:34 -07:00
635f4e42ff
Add detailed doc on source allocation/filtering
Hansung Kim
2023-10-25 20:55:01 -07:00
6371cdc03c
Use edge.hasData instead of TLUtils in adapter
Hansung Kim
2023-10-25 20:28:01 -07:00
1e8cc5ef90
Bump vortex
Hansung Kim
2023-10-25 20:07:20 -07:00
d70cbc8e58
Do matchingSources filtering using Vortex tag instead of TL source
Hansung Kim
2023-10-25 19:48:21 -07:00
78e193db42
Add safety assert on sourceWidth
Hansung Kim
2023-10-25 18:17:03 -07:00
09f512fda7
Don't reply write requests from Vortex core
Hansung Kim
2023-10-25 13:08:18 -07:00
ba8bed6120
Set missing opcode field for uncoalesced requests
Hansung Kim
2023-10-25 13:07:54 -07:00
762e6dfd27
Rename queueDepth -> reqQueueDepth
Hansung Kim
2023-10-25 11:29:51 -07:00
f0a401d72b
Add missing PutPartial mask handling for coalesced writes
Hansung Kim
2023-10-24 15:11:41 -07:00
3fc3e91831
Rename & doc
Hansung Kim
2023-10-24 14:04:00 -07:00
8affa755d0
Remove overly strict enq.ready assertion on respQueues
Hansung Kim
2023-10-24 11:37:49 -07:00
e9c206dfa2
Properly handle upstream and downstream backpressure for respQueues
Hansung Kim
2023-10-24 11:36:18 -07:00
8e0904a1ad
Fix matchingSources logic when all lanes are invalid
Hansung Kim
2023-10-23 22:10:10 -07:00
a14d8b6814
Properly handle TL dataWidth mismatch for core-to-sbus configs
Hansung Kim
2023-10-23 20:32:36 -07:00
2e37d2ce3f
Only check opcode validity when fire
Hansung Kim
2023-10-23 20:31:00 -07:00
0f9896e001
Instantiate coalescer inside VortexTile
Hansung Kim
2023-10-23 15:01:03 -07:00
2091ef686b
Rename defaultConfig -> DefaultCoalescerConfig
Hansung Kim
2023-10-23 14:50:15 -07:00
105bb37421
Make VortexCoreParams; bring VortexTile into rocketchip.tile
Hansung Kim
2023-10-23 13:04:48 -07:00
f4553ffdb1
Remove done TODO
Hansung Kim
2023-10-23 11:33:38 -07:00
60a63d4e11
FatBank Integration Improvements: 1. ensure FatBank prioritze Ack read over Ack write to downstream coalescer 2. Between FatBank and L2, use the new sourceGenerator to allow both Read and Write Reqs sharing the same pool of available src_ids
Vamber Yang
2023-10-22 17:03:37 -07:00
2a9f2f8421
fix typo
Richard Yan
2023-10-19 17:10:56 -07:00
9d8e9de8d0
differentiate addresses for different harts
Richard Yan
2023-10-19 16:14:35 -07:00
805abd1b4b
Bump vortex for TL port change
Hansung Kim
2023-10-18 20:05:55 -07:00
ff302c1ba5
Use VortexTLAdapter for useVxCache = true as well
Hansung Kim
2023-10-18 20:04:31 -07:00
0d92eb65d4
Increase sourceWidth to fix vx_wspawn sync bug
Hansung Kim
2023-10-18 15:19:11 -07:00
fb97bd3c2b
Decouple Vortex imem bundle from TL
Hansung Kim
2023-10-17 12:18:58 -07:00
e4dd0c21e9
Bump vortex
Hansung Kim
2023-10-16 20:45:18 -07:00
8ab0529354
Move VortexBundleA/D to Core; resolve TODOs
Hansung Kim
2023-10-16 17:54:12 -07:00
eb9772b750
Decouple Vortex dmem bundle from TL
Hansung Kim
2023-10-16 17:42:17 -07:00
db8625fb20
Simplify metadata type wrangling in SourceGen
Hansung Kim
2023-10-16 15:24:37 -07:00
154e61b1a3
Fix SourceGen metadata IO errors in coalescer
Hansung Kim
2023-10-16 11:43:20 -07:00
e50903ed42
VX_FatBank runs in SoC Config with Coalescer till termination Issues addressed: 1. FatBank ack to downstream coalescer with the correct size on ChannelD 2. FatBank ack to downstream coalescer immediately after W Req 3. FatBank generates unique ID for W Req to L2 4. Allows coalescer to config max Coal to L1 ReadSize at compile time
Vamber Yang
2023-10-16 10:31:31 -07:00
630d76461c
Do proper TL sourceId allocation for Vortex dmem requests
Hansung Kim
2023-10-16 01:12:33 -07:00
c34853447b
Implement metadata retrieval in SourceGenerator
Hansung Kim
2023-10-16 01:11:50 -07:00
5b356b735c
Fix unused warning in Coalescing
Hansung Kim
2023-10-15 23:24:32 -07:00
78012800e7
Clarify confusing in/outResp naming in SourceGenerator
Hansung Kim
2023-10-15 23:17:01 -07:00
cbd32b78a9
add metadata field in SourceGenerator table
Hansung Kim
2023-10-15 22:56:07 -07:00
ff4fc66c56
Reformat
Hansung Kim
2023-10-15 01:17:20 -07:00
dd194ca61d
bump vortex
Richard Yan
2023-10-13 15:25:49 -07:00
7c5281cd0e
multilane support, args.bin ROM, verilog sources cleanup and vortex bump
Richard Yan
2023-09-15 11:16:55 -07:00
d392d76608
bump vortex and increase source ids
Richard Yan
2023-09-11 14:06:08 -07:00
43f95175f1
bump verilog sources, remove files and mem changes
Richard Yan
2023-09-09 01:55:02 -07:00
8cef2ae135
integrate vortex as tile
Richard Yan
2023-09-08 14:25:37 -07:00
a424f92b55
Make MemTraceDriver no longer be UnitTestModule
Hansung Kim
2023-08-23 19:02:43 -07:00
af9205ce85
Add missing io.finished to fix elaboration
Hansung Kim
2023-08-23 17:56:51 -07:00
0fa14b7661
Use cf-interpolator for simulation-time string
Hansung Kim
2023-08-23 17:44:57 -07:00
218e3cad92
Rename TracerSystemMem -> CanHaveMemtraceCore
Hansung Kim
2023-07-22 16:27:47 -07:00
f8a1a28c6c
Pretty-print CoalescingUnit configs at elaboration time
Hansung Kim
2023-07-22 16:18:02 -07:00
a2bddfe8a8
Fix connecting to sbus to use updated BusWrapper API
Hansung Kim
2023-07-22 15:13:42 -07:00
2f6da70af9
Add TODO-to-move to TracerSystemMem
Hansung Kim
2023-07-22 12:57:19 -07:00
bcb11ee0fb
Remove old fixmes and todos
Hansung Kim
2023-05-28 22:59:18 -07:00
74a8a81f82
Revert to respQueueDepth = 4
Hansung Kim
2023-05-28 22:38:01 -07:00
e40b7f0b8b
Support receiving trace filename from VPI for loggers
Hansung Kim
2023-05-28 22:15:32 -07:00
af01e39b5a
Revamp dataflow between uncoalescer and inflight table
Hansung Kim
2023-05-27 13:59:25 -07:00
aada78da33
Fix writing to inflight table when valid not fire
Hansung Kim
2023-05-27 13:02:00 -07:00
da3cfa9bd9
Minor doc
Hansung Kim
2023-05-21 11:21:51 -07:00
5491491a6b
Fix newSrcId truncation in InFlightTableEntry
Hansung Kim
2023-05-21 02:50:04 -07:00
1d6d35233f
Move multi-beat warning to inside param class
Hansung Kim
2023-05-20 00:44:27 -07:00
7c7752a5a2
Disable uncoalescer unit test temporarily
Hansung Kim
2023-05-20 00:23:18 -07:00
1243fd75a2
Fix old param name in XBarUnitTest
Hansung Kim
2023-05-20 00:22:40 -07:00
2a0fd24d17
Make SourceGenerator do CAM search for lowest-index free slot
Hansung Kim
2023-05-19 23:52:35 -07:00
9ecace676c
Add useful error msg
Vamber Yang
2023-05-19 17:47:40 -07:00
0d96d81968
Make numOldSrcIds and numNewSrcIds parameters of SoC
Vamber Yang
2023-05-19 17:47:18 -07:00
ab3ce82aff
Fixed MemTracerDriverImpr to generate the last request when SimMemTrace outputs finished signal
Vamber Yang
2023-05-19 05:03:13 -07:00
d88a734aee
Fixed MemTracerDriverImp to only terminate when all outstanding reqs are reclaimed This is for slightly more accurate perf numbers.
Vamber Yang
2023-05-19 03:16:52 -07:00
d234b8c09a
Add RTL for Coalescer Priority XBar and relevant keys&configs for SoC Integration
Vamber Yang
2023-05-16 20:22:49 -07:00
ebf81babc1
Modified WithCoalescer to dynamically configure databusWidth and MaxCoalSize according to underlying SoC setting, This makes running perf numbers easier
Vamber Yang
2023-05-16 05:57:35 -07:00
Hansung Kim