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  • 8ed82e8261 Remove unclear size width requirement in tl adapter Hansung Kim 2023-11-27 16:42:07 -08:00
  • dafacf9873 Bump vortex Hansung Kim 2023-11-19 17:55:23 -08:00
  • ccd6582991 Set correct mask for PutPartial for core writes Hansung Kim 2023-11-19 17:54:08 -08:00
  • d7cbf4916a Rename sourceWidth -> tagWidth Hansung Kim 2023-11-19 17:49:47 -08:00
  • 1346f74210 Bump vortex with tag width fix Hansung Kim 2023-11-17 19:13:48 -08:00
  • 765c8ef1b0 Remove unnecessary write ack filtering logic in VortexTLAdapter Hansung Kim 2023-11-17 19:12:35 -08:00
  • 6802d23598 Change dcache sourceWidth constant to match DCACHE_NOSM_TAG_WIDTH Hansung Kim 2023-11-17 19:12:03 -08:00
  • 05ffa884a6 Bump vortex with DCR fix Hansung Kim 2023-11-16 18:00:56 -08:00
  • 65f4264d57 Pass hang100 address to wrapper verilog Hansung Kim 2023-11-16 18:00:40 -08:00
  • dca74eface Bump vortex to 2.0 Hansung Kim 2023-11-15 22:06:17 -08:00
  • 134dd4eb59 Update BlackBox to include Vortex 2.0 Hansung Kim 2023-11-15 21:58:40 -08:00
  • 0768a7abc9 More cleanup and doc Hansung Kim 2023-11-10 18:49:11 -08:00
  • 0bb8e6d705 Bump vortex with ibuffer size fix Hansung Kim 2023-11-10 18:38:59 -08:00
  • ecfa18ce69 Rename to VortexBank Hansung Kim 2023-11-10 17:46:04 -08:00
  • 78e09160a2 Rename L1System -> VortexL1; do not expose bank Xbar from L1 Hansung Kim 2023-11-10 16:11:43 -08:00
  • 257232dec8 Require MSHR size matches nSrcId to L2 Hansung Kim 2023-11-10 15:04:32 -08:00
  • 5adf334af4 Scalafmt & rename & update doc Hansung Kim 2023-11-10 14:58:16 -08:00
  • d51ce4cfa8 Reformat Hansung Kim 2023-11-10 14:46:33 -08:00
  • 17a39a369f Cleanup conditional L1 instantiation Hansung Kim 2023-11-10 14:42:33 -08:00
  • a0c15b2cc3 Use separate {imem,dmem}SourceWidth to fix deadlock Hansung Kim 2023-11-08 20:20:17 -08:00
  • 2f205be702 Update docs Hansung Kim 2023-11-08 14:02:25 -08:00
  • 571d33a5de Remove unused MSB offset code from get getCoalescedDataChunk Hansung Kim 2023-11-06 13:40:25 -08:00
  • 61aad0315c L1 FatBank Integration, multi-bank working with 4 dcache banks, 1 icache bank Vamber Yang 2023-11-06 20:51:54 -08:00
  • e958ede277 multi-bank working when nBanks=2, encountered a putPartial error, need to pull latest change Vamber Yang 2023-11-06 20:51:23 -08:00
  • be5134cd8a L1 fatbank works with 2^5 source bits in SourceGen, failed with < 2^4 source bits in SourceGen Vamber Yang 2023-11-01 23:48:24 -07:00
  • d2bfc31592 Fix store opcode assertion in AOpcodeIsStore Hansung Kim 2023-10-31 23:06:35 -07:00
  • 75adb1dc66 Intergation of L1 Fatbank Vamber Yang 2023-10-31 16:14:34 -07:00
  • 635f4e42ff Add detailed doc on source allocation/filtering Hansung Kim 2023-10-25 20:55:01 -07:00
  • 6371cdc03c Use edge.hasData instead of TLUtils in adapter Hansung Kim 2023-10-25 20:28:01 -07:00
  • 1e8cc5ef90 Bump vortex Hansung Kim 2023-10-25 20:07:20 -07:00
  • d70cbc8e58 Do matchingSources filtering using Vortex tag instead of TL source Hansung Kim 2023-10-25 19:48:21 -07:00
  • 78e193db42 Add safety assert on sourceWidth Hansung Kim 2023-10-25 18:17:03 -07:00
  • 09f512fda7 Don't reply write requests from Vortex core Hansung Kim 2023-10-25 13:08:18 -07:00
  • ba8bed6120 Set missing opcode field for uncoalesced requests Hansung Kim 2023-10-25 13:07:54 -07:00
  • 762e6dfd27 Rename queueDepth -> reqQueueDepth Hansung Kim 2023-10-25 11:29:51 -07:00
  • f0a401d72b Add missing PutPartial mask handling for coalesced writes Hansung Kim 2023-10-24 15:11:41 -07:00
  • 3fc3e91831 Rename & doc Hansung Kim 2023-10-24 14:04:00 -07:00
  • 8affa755d0 Remove overly strict enq.ready assertion on respQueues Hansung Kim 2023-10-24 11:37:49 -07:00
  • e9c206dfa2 Properly handle upstream and downstream backpressure for respQueues Hansung Kim 2023-10-24 11:36:18 -07:00
  • 8e0904a1ad Fix matchingSources logic when all lanes are invalid Hansung Kim 2023-10-23 22:10:10 -07:00
  • a14d8b6814 Properly handle TL dataWidth mismatch for core-to-sbus configs Hansung Kim 2023-10-23 20:32:36 -07:00
  • 2e37d2ce3f Only check opcode validity when fire Hansung Kim 2023-10-23 20:31:00 -07:00
  • 0f9896e001 Instantiate coalescer inside VortexTile Hansung Kim 2023-10-23 15:01:03 -07:00
  • 2091ef686b Rename defaultConfig -> DefaultCoalescerConfig Hansung Kim 2023-10-23 14:50:15 -07:00
  • 105bb37421 Make VortexCoreParams; bring VortexTile into rocketchip.tile Hansung Kim 2023-10-23 13:04:48 -07:00
  • f4553ffdb1 Remove done TODO Hansung Kim 2023-10-23 11:33:38 -07:00
  • 60a63d4e11 FatBank Integration Improvements: 1. ensure FatBank prioritze Ack read over Ack write to downstream coalescer 2. Between FatBank and L2, use the new sourceGenerator to allow both Read and Write Reqs sharing the same pool of available src_ids Vamber Yang 2023-10-22 17:03:37 -07:00
  • 2a9f2f8421 fix typo Richard Yan 2023-10-19 17:10:56 -07:00
  • 77e3ad4934 Merge branch 'graphics' of https://github.com/hansungk/rocket-chip into graphics Richard Yan 2023-10-19 16:16:24 -07:00
  • 9d8e9de8d0 differentiate addresses for different harts Richard Yan 2023-10-19 16:14:35 -07:00
  • 805abd1b4b Bump vortex for TL port change Hansung Kim 2023-10-18 20:05:55 -07:00
  • ff302c1ba5 Use VortexTLAdapter for useVxCache = true as well Hansung Kim 2023-10-18 20:04:31 -07:00
  • 0d92eb65d4 Increase sourceWidth to fix vx_wspawn sync bug Hansung Kim 2023-10-18 15:19:11 -07:00
  • fb97bd3c2b Decouple Vortex imem bundle from TL Hansung Kim 2023-10-17 12:18:58 -07:00
  • e4dd0c21e9 Bump vortex Hansung Kim 2023-10-16 20:45:18 -07:00
  • 8ab0529354 Move VortexBundleA/D to Core; resolve TODOs Hansung Kim 2023-10-16 17:54:12 -07:00
  • eb9772b750 Decouple Vortex dmem bundle from TL Hansung Kim 2023-10-16 17:42:17 -07:00
  • db8625fb20 Simplify metadata type wrangling in SourceGen Hansung Kim 2023-10-16 15:24:37 -07:00
  • 154e61b1a3 Fix SourceGen metadata IO errors in coalescer Hansung Kim 2023-10-16 11:43:20 -07:00
  • e50903ed42 VX_FatBank runs in SoC Config with Coalescer till termination Issues addressed: 1. FatBank ack to downstream coalescer with the correct size on ChannelD 2. FatBank ack to downstream coalescer immediately after W Req 3. FatBank generates unique ID for W Req to L2 4. Allows coalescer to config max Coal to L1 ReadSize at compile time Vamber Yang 2023-10-16 10:31:31 -07:00
  • 630d76461c Do proper TL sourceId allocation for Vortex dmem requests Hansung Kim 2023-10-16 01:12:33 -07:00
  • c34853447b Implement metadata retrieval in SourceGenerator Hansung Kim 2023-10-16 01:11:50 -07:00
  • 5b356b735c Fix unused warning in Coalescing Hansung Kim 2023-10-15 23:24:32 -07:00
  • 78012800e7 Clarify confusing in/outResp naming in SourceGenerator Hansung Kim 2023-10-15 23:17:01 -07:00
  • cbd32b78a9 add metadata field in SourceGenerator table Hansung Kim 2023-10-15 22:56:07 -07:00
  • ff4fc66c56 Reformat Hansung Kim 2023-10-15 01:17:20 -07:00
  • dd194ca61d bump vortex Richard Yan 2023-10-13 15:25:49 -07:00
  • 8d479438b1 Merge branch 'graphics' of https://github.com/hansungk/rocket-chip into graphics Richard Yan 2023-10-13 14:04:20 -07:00
  • dfae96ec9d add wait register Richard Yan 2023-10-13 13:31:14 -07:00
  • b7a7a7a0a7 Bump vortex Hansung Kim 2023-10-11 20:32:08 -07:00
  • dab1d907d6 Comment out hartid and fpu from VortexBundle Hansung Kim 2023-10-11 20:29:15 -07:00
  • acc66e413a Set Vortex CORE_ID parameter using Tile hartId Hansung Kim 2023-10-11 20:28:04 -07:00
  • 127d7613e1 add vortex fat bank + test (not compiling atm) joshua 2023-10-09 14:49:57 -07:00
  • c368e92ddb Bump vortex Hansung Kim 2023-10-06 21:31:22 -07:00
  • 1de8a4ffa8 Update doc comments Hansung Kim 2023-10-05 16:38:12 -07:00
  • e7a008ec74 Rename #define constants in SimMemTrace Hansung Kim 2023-10-01 20:58:49 -07:00
  • 5bf068306f Fix too large bitwidth error in Verilator Hansung Kim 2023-10-01 20:57:46 -07:00
  • 5ee4154f26 Fix C/verilog argument size mismatch on Verilator Hansung Kim 2023-10-01 12:10:14 -07:00
  • a98ec2758e bump vortex joshua 2023-09-29 00:52:23 -07:00
  • 3566159c12 Merge remote-tracking branch 'origin/graphics' into vx_cache joshua 2023-09-28 11:38:05 -07:00
  • f0f395661d bump vortex Richard Yan 2023-09-27 10:53:38 -07:00
  • c403156127 fix merge errors (?) joshua 2023-09-25 23:40:29 -07:00
  • 0f47ae078e add operand roms, bump vortex Richard Yan 2023-09-25 21:27:13 -07:00
  • c5bfb66ee5 it works joshua 2023-09-24 17:43:00 -07:00
  • 6a6f7fcaf0 still not working joshua 2023-09-24 13:28:29 -07:00
  • 63aee46908 still not sure what error is joshua 2023-09-23 17:52:02 -07:00
  • e3f85da12c add vortex cache temporarily joshua 2023-09-23 13:03:53 -07:00
  • 7c5281cd0e multilane support, args.bin ROM, verilog sources cleanup and vortex bump Richard Yan 2023-09-15 11:16:55 -07:00
  • d392d76608 bump vortex and increase source ids Richard Yan 2023-09-11 14:06:08 -07:00
  • 43f95175f1 bump verilog sources, remove files and mem changes Richard Yan 2023-09-09 01:55:02 -07:00
  • 8cef2ae135 integrate vortex as tile Richard Yan 2023-09-08 14:25:37 -07:00
  • a424f92b55 Make MemTraceDriver no longer be UnitTestModule Hansung Kim 2023-08-23 19:02:43 -07:00
  • af9205ce85 Add missing io.finished to fix elaboration Hansung Kim 2023-08-23 17:56:51 -07:00
  • 0fa14b7661 Use cf-interpolator for simulation-time string Hansung Kim 2023-08-23 17:44:57 -07:00
  • 218e3cad92 Rename TracerSystemMem -> CanHaveMemtraceCore Hansung Kim 2023-07-22 16:27:47 -07:00
  • f8a1a28c6c Pretty-print CoalescingUnit configs at elaboration time Hansung Kim 2023-07-22 16:18:02 -07:00
  • a2bddfe8a8 Fix connecting to sbus to use updated BusWrapper API Hansung Kim 2023-07-22 15:13:42 -07:00
  • 2f6da70af9 Add TODO-to-move to TracerSystemMem Hansung Kim 2023-07-22 12:57:19 -07:00
  • bcb11ee0fb Remove old fixmes and todos Hansung Kim 2023-05-28 22:59:18 -07:00
  • 74a8a81f82 Revert to respQueueDepth = 4 Hansung Kim 2023-05-28 22:38:01 -07:00