Make numOldSrcIds and numNewSrcIds parameters of SoC

src/main/scala/tilelink/Coalescing.scala

@@ -11,7 +11,9 @@ import freechips.rocketchip.util.MultiPortQueue
 import freechips.rocketchip.unittest._
 
 // TODO: find better place for these
-case class SIMTCoreParams(nLanes: Int = 4)
+
+// Note: numNewSrcId is not a part of CoreParam, because the SIMT core should be agnostic to how inflight coalesced request can be genertated
+case class SIMTCoreParams(nLanes: Int = 4, nSrcIds: Int = 8)
 case class MemtraceCoreParams(tracefilename: String = "undefined", traceHasSource: Boolean = false)
 case class CoalXbarParam()
 

src/main/scala/tilelink/TracerSystemMem.scala

@@ -12,7 +12,10 @@ trait CanHaveMemtraceCore { this: BaseSubsystem =>
   p(MemtraceCoreKey).map { param =>
     // Safe to use get as WithMemtraceCore requires WithNLanes to be defined
     val simtParam = p(SIMTCoreKey).get
-    val config = defaultConfig.copy(numLanes = simtParam.nLanes)
+    val config = defaultConfig.copy(
+      numLanes = simtParam.nLanes, 
+      numOldSrcIds = simtParam.nSrcIds
+      )
     val numLanes = simtParam.nLanes
     val filename = param.tracefilename
     val tracer = LazyModule(
@@ -33,6 +36,7 @@ trait CanHaveMemtraceCore { this: BaseSubsystem =>
       case Some(coalParam) => {
         val coal = LazyModule(new CoalescingUnit(coalParam))
         println(s"============ CoalescingUnit instantiated [numLanes=${coalParam.numLanes}]")
+        println(s"============ numOldSrcId and numNewSrc are (${coalParam.numOldSrcIds},${coalParam.numNewSrcIds})")
         coal.cpuNode :=* coreSideLogger.node :=* tracer.node // N lanes
         memSideLogger.node :=* coal.aggregateNode            // N+1 lanes
         memSideLogger.node