Coalescer XBar, a design overhaul from CoalArbiter, the best way to implement the 'arbiter' functionality is to implement as a TLXbar with different arbitration policy (RR + PO)
This commit is contained in:
Vamber Yang
@@ -1756,64 +1756,64 @@ class TLRAMCoalescerTest(timeout: Int = 500000)(implicit p: Parameters) extends
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////////////
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////////////
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////////////
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//////////// Code for CoalArbiter
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//////////// Code for CoalescerXbar
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////////////
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////////////
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// Lazy Module is needed to instantiate outgoing node
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class CoalArbiter(config: CoalescerConfig) (implicit p: Parameters) extends LazyModule {
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class CoalescerXbar(config: CoalescerConfig) (implicit p: Parameters) extends LazyModule {
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// Let SIMT's word size be 32, and read/write granularity be 256
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val fullSourceIdRange = config.numOldSrcIds * config.numLanes + config.numNewSrcIds * config.numCoalReqs
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// K client nodes of edge size 32 for non-coalesced reqs
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val nonCoalNarrowNodes = Seq.tabulate(config.numArbiterOutputPorts){ i =>
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// 32 client nodes of edge size 32 for non-coalesced reqs
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// And attaching them wigets
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val nonCoalNarrowNodes = Seq.tabulate(config.numLanes){i =>
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val nonCoalNarrowParam = Seq(
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TLMasterParameters.v1(
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name = "NonCoalNarrowNode" + i.toString,
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sourceId = IdRange(0, fullSourceIdRange)
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sourceId = IdRange(0, config.numOldSrcIds)
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)
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)
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TLClientNode(Seq(TLMasterPortParameters.v1(nonCoalNarrowParam)))
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}
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val nonCoalWidgets = Seq.tabulate(config.numLanes){ _=>
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TLWidthWidget(config.wordSizeInBytes)
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}
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(nonCoalWidgets zip nonCoalNarrowNodes).foreach{
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case(wgt,node)=> wgt := node
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}
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//Creating a round robin cross tilelink xbar for the un-coalesced
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//and connect them to the widgets
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val nonCoalXbar = LazyModule(new TLXbar(TLArbiter.roundRobin))
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nonCoalWidgets.foreach{nonCoalXbar.node:=_}
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// One identity Node for the Noncoalesced Reqest after Width Adaptation
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// You can put widget between idenity node and client node (diplomacy)
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val nonCoalNode = TLIdentityNode()
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nonCoalNarrowNodes.foreach(narrowNode =>
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nonCoalNode := TLWidthWidget(config.wordSizeInBytes) := narrowNode
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)
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// K client nodes of edge size 256 for the coalesced reqs
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val coalReqNodes = Seq.tabulate(config.numArbiterOutputPorts){ i =>
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val coalReqNodes = Seq.tabulate(config.numCoalReqs){ i =>
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val coalParam = Seq(
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TLMasterParameters.v1(
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name = "CoalReqNode" + i.toString,
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sourceId = IdRange(0, fullSourceIdRange)
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sourceId = IdRange(0, config.numNewSrcIds)
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)
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)
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TLClientNode(Seq(TLMasterPortParameters.v1(coalParam)))
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}
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// 1 idenity node for the Coalesced Reqs
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val coalNode = TLIdentityNode()
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coalReqNodes.foreach(coalReqNode =>
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coalNode := coalReqNode
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)
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// Create a RR Xbar for the coalesced request
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val coalXbar = LazyModule(new TLXbar(TLArbiter.roundRobin))
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coalReqNodes.foreach{coalXbar.node:=_}
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//Assertion Section
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def isPowerOfTwo(n: Int): Boolean = {
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(n > 0) && ((n & (n - 1)) == 0)
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}
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assert(isPowerOfTwo(config.numOldSrcIds), "Number of old source id must be power of 2")
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assert(isPowerOfTwo(config.numNewSrcIds), "Number of new source id must be power of 2")
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//Below is for efficient conversion from Global to Local bits
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//Also, we should have more source id for coalesced request for better perf
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assert(config.numNewSrcIds >= config.numOldSrcIds, "new source id must be equal or greater than old source id")
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// 1 Final Output Identity Node
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val outputNode = TLIdentityNode()
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//Create a Priority XBar between Coalesced and Uncoalesced Request
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val outputXbar = LazyModule(new TLXbar(TLArbiter.lowestIndexFirst))
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outputXbar.node :=* coalXbar.node
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outputXbar.node :=* nonCoalXbar.node
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//express output crossbar as an idenity node for simpler downstream connection
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val node = TLIdentityNode()
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node :=* outputXbar.node
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val nonCoalEntryT = new ReqQueueEntry(
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log2Ceil(config.numOldSrcIds),
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config.wordWidth,
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@@ -1835,14 +1835,14 @@ class CoalArbiter(config: CoalescerConfig) (implicit p: Parameters) extends Lazy
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val respCoalBundleT = new CoalescedResponseBundle(config)
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lazy val module = new CoalArbiterImpl(
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lazy val module = new CoalescerXbarImpl(
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this, config, nonCoalEntryT, coalEntryT, respNonCoalEntryT, respCoalBundleT)
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}
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class CoalArbiterImpl(outer: CoalArbiter,
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class CoalescerXbarImpl(outer: CoalescerXbar,
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config: CoalescerConfig,
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nonCoalEntryT: ReqQueueEntry,
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coalEntryT: ReqQueueEntry,
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@@ -1859,119 +1859,7 @@ class CoalArbiterImpl(outer: CoalArbiter,
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}
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)
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//Helper Class & Method Section
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//Provide an simple decoupled interface between bundle of 2 different type
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class ConverterTunnel[T <: Data, U <: Data](
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genA: T,
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genB: U,
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conversionFn: T => U
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) extends Module {
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val io = IO(new Bundle {
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val in = Flipped(Decoupled(genA.cloneType))
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val out = Decoupled(genB.cloneType)
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})
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io.in.ready := io.out.ready
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io.out.valid := io.in.valid
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io.out.bits := conversionFn(io.in.bits)
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}
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def canHitBank(addr: UInt, bankNum: UInt) : Bool = {
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val byteOffset = 3
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val bankBase = log2Ceil(config.bankStrideInBytes)
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val bankOffset = log2Ceil(config.numArbiterOutputPorts)
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(addr(bankBase+bankOffset-byteOffset, bankBase - byteOffset) === bankNum)
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}
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//This Operation Could be Expensive
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def toGlobalSourceId(isCoalReq : Bool, laneIdx : UInt, sourceID : UInt) : UInt = {
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val gid = Mux(isCoalReq,
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config.numNewSrcIds.U * laneIdx + sourceID,
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config.numOldSrcIds.U * laneIdx + sourceID + config.numNewSrcIds.U * config.numCoalReqs.U
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)
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gid
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}
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//All the ids are power of 2, so we can just look at bottom bits
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def toLocalSourceId(isCoalReq : Bool, sourceID : UInt) : UInt = {
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val sid = Mux(isCoalReq,
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sourceID(log2Ceil(config.numNewSrcIds)-1, 0),
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sourceID(log2Ceil(config.numOldSrcIds)-1, 0)
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)
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sid
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}
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def belongsToLane(laneIdx: UInt, gid: UInt) : Bool = {
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val base = config.numNewSrcIds.U * config.numCoalReqs.U
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((gid >= base + config.numOldSrcIds.U * laneIdx) &&
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(gid < base + config.numOldSrcIds.U * (laneIdx+1.U)))
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}
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def isCoalReq(gid : UInt) : Bool = {
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gid <= config.numNewSrcIds.U * config.numCoalReqs.U
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}
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//
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val fullSourceIdRange = config.numOldSrcIds * config.numLanes + config.numNewSrcIds * config.numCoalReqs
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val nonCoalGiDEntryT = new ReqQueueEntry(
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log2Ceil(fullSourceIdRange),
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config.wordWidth,
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config.addressWidth,
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log2Ceil(config.wordSizeInBytes)
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)
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val coalGiDEntryT = new ReqQueueEntry(
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log2Ceil(fullSourceIdRange),
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log2Ceil(config.maxCoalLogSize),
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config.addressWidth,
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config.maxCoalLogSize //already log 2
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)
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// Before either a coalesced or non coalesced request enter RR arbiter
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// It needs to turn its source into global source id
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// Unfortunately this involves extending the width of sourceid field, and a new bundle must be created
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// This is a higher order function
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def reqEntry2GidReqFn(laneIndex : UInt, reqEntryT : ReqQueueEntry, isCoalReq : Bool) : ReqQueueEntry => ReqQueueEntry = {
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def func(lid_req : ReqQueueEntry) : ReqQueueEntry = {
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val gid_req = reqEntryT.cloneType
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gid_req <> lid_req
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gid_req.source := toGlobalSourceId(isCoalReq, laneIndex, lid_req.source)
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gid_req
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}
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func
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}
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def reqEntry2TLAFn(edgeOut: TLEdgeOut) : ReqQueueEntry => TLBundleA = {
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def func(gid_req : ReqQueueEntry) : TLBundleA = {
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gid_req.toTLA(edgeOut)
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}
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func
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}
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def tlD2respEntryFn() : TLBundleD => RespQueueEntry = {
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def func(bundle: TLBundleD) : RespQueueEntry = {
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val resp = Wire(respNonCoalEntryT)
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resp.fromTLD(bundle)
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resp.source := toLocalSourceId(false.B, bundle.source)
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resp
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}
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func
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}
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def tlD2CoalBundleFn() : TLBundleD => CoalescedResponseBundle = {
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def func(bundle: TLBundleD) : CoalescedResponseBundle = {
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val coalbundle = Wire(respCoalBundleT)
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coalbundle.fromTLD(bundle)
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coalbundle.source := toLocalSourceId(true.B, bundle.source)
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coalbundle
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}
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func
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}
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/////////////////////////////////////////////////////
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//HDL Implementation Section
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/////////////////////////////////////////////////////
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//Create Queues to receive data from upstream
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//Stage 1: Create Queue for nonCoalReqs and CoalReqs
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val nonCoalReqsQueues = Seq.tabulate(config.numLanes){_=>
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Module(new Queue(nonCoalEntryT.cloneType, 1, true, false))
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@@ -1980,182 +1868,53 @@ class CoalArbiterImpl(outer: CoalArbiter,
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Module(new Queue(coalEntryT.cloneType, 1, true, false))
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}
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//Stage 1a: connect two Queue groups to the input
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(io.nonCoalReqs zip nonCoalReqsQueues).foreach{
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(io.nonCoalReqs++io.coalReqs zip nonCoalReqsQueues++coalReqsQueues).foreach{
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case (req, q) => q.io.enq <> req
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}
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(io.coalReqs zip coalReqsQueues).foreach{
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case (req, q) => q.io.enq <> req
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//Stage 2: connect output of the queue to the respective Node
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(nonCoalReqsQueues++coalReqsQueues zip outer.nonCoalNarrowNodes++outer.coalReqNodes).foreach{
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case(q, node) =>
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val (tlOut, edgeOut) = node.out(0)
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q.io.deq.ready := tlOut.a.ready
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tlOut.a.valid := q.io.deq.valid
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tlOut.a.bits := q.io.deq.bits.toTLA(edgeOut)
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}
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//Stage 1b: connect output of Queues to the RR arbiters (each arbiter is for a unique bank)
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// the two loops below could be merged into one loop, but separated for readability
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val nonCoalRRArbiters = Seq.tabulate(config.numArbiterOutputPorts){_=>
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Module(new RRArbiter(nonCoalGiDEntryT.cloneType, config.numLanes))
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}
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nonCoalReqsQueues.zipWithIndex.foreach{ case(q, q_idx) =>
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nonCoalRRArbiters.zipWithIndex.foreach{ case(arb, arb_idx) =>
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val nonCoal2gidFunc = reqEntry2GidReqFn(q_idx.U, nonCoalGiDEntryT, false.B)
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val nonCoalRRArbTunnel = Module(new ConverterTunnel(
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nonCoalEntryT.cloneType,
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nonCoalGiDEntryT.cloneType,
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nonCoal2gidFunc)
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)
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nonCoalRRArbTunnel.io.in <> q.io.deq
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arb.io.in(q_idx) <> nonCoalRRArbTunnel.io.out
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//OverWrite Valid base on if we can actually hit this bank
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arb.io.in(q_idx).valid := canHitBank(nonCoalRRArbTunnel.io.out.bits.address, arb_idx.U) &&
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nonCoalRRArbTunnel.io.out.valid
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}
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}
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val coalRRArbiters = Seq.tabulate(config.numArbiterOutputPorts){_=>
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Module(new RRArbiter(coalGiDEntryT.cloneType, config.numCoalReqs))
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}
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coalReqsQueues.zipWithIndex.foreach{ case(q, q_idx) =>
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coalRRArbiters.zipWithIndex.foreach{ case(arb, arb_idx) =>
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val coal2gidFunc = reqEntry2GidReqFn(q_idx.U, coalGiDEntryT, true.B)
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val coalRRArbTunnel = Module(new ConverterTunnel(
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coalEntryT.cloneType,
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coalGiDEntryT.cloneType,
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coal2gidFunc)
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)
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coalRRArbTunnel.io.in <> q.io.deq
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arb.io.in(q_idx) <> coalRRArbTunnel.io.out
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//OverWrite Valid
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arb.io.in(q_idx).valid := canHitBank(coalRRArbTunnel.io.out.bits.address, arb_idx.U) &&
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coalRRArbTunnel.io.out.valid
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}
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//The XBar will take care of the rest
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//
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// Inward data handling
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//
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// For the uncoalesced data response
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(outer.nonCoalNarrowNodes zip io.nonCoalResps).foreach{
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case(node,resp) =>
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val (tlOut, edgeOut) = node.out(0)
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val nonCoalResp = Wire(respNonCoalEntryT)
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nonCoalResp.fromTLD(tlOut.d.bits)
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tlOut.d.ready := resp.ready
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resp.valid := tlOut.d.valid
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resp.bits := nonCoalResp
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}
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//Stage 2, Connect the output of Arbiters to respective nonCoal node
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// Concatenate the nodes , concatenates the arbiters, and zip them together, then loop
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// the reqEntry2TLA will generate different TLA bundle depending on if the Req is coal or non coal
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((outer.nonCoalNarrowNodes++outer.coalReqNodes) zip
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(nonCoalRRArbiters++coalRRArbiters)).foreach{
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case (node, arb) =>
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val (tlOut, edgeOut) = node.out(0)
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val coal2TLAFunc = reqEntry2TLAFn(edgeOut)
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val nonCoalTLATunnel = Module(new ConverterTunnel(
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arb.io.out.bits.cloneType,
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tlOut.a.bits.cloneType,
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coal2TLAFunc
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)
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)
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nonCoalTLATunnel.io.in <> arb.io.out
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tlOut.a <> nonCoalTLATunnel.io.out
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}
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//Stage 3, Make the Idenity node pass through channel A
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// Connect the K edges Identity Node to PO arbiter
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// noncoalesced to port 1, coalesced to port 0
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val priorityArbs = Seq.tabulate(config.numArbiterOutputPorts){_=>
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Module(new Arbiter(outer.outputNode.out(0)._1.a.bits.cloneType, 2))
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}
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//Make both Idenity node Pass Through Channel A, for both Coal and NonCoal
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((outer.nonCoalNode.out ++ outer.coalNode.out) zip
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(outer.nonCoalNode.in ++ outer.coalNode.in)).foreach{
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case ((tlOut,_),(tlIn,_)) =>
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tlOut.a <> tlIn.a
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}
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//Connection to PO Arbiters
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((outer.nonCoalNode.out zip outer.coalNode.out) zip priorityArbs).foreach{
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case (((nonCoalOut, _),(coalOut, _)), arb) =>
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arb.io.in(1) <> nonCoalOut.a
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arb.io.in(0) <> coalOut.a
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}
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//Stage 4, Connect PO arbiter to each edge of output Node
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//And make idenitity node passs through the inputs
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((outer.outputNode.in zip outer.outputNode.out) zip priorityArbs).foreach{
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case (((tlIn, _), (tlOut, _)), arb) =>
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tlOut.a <> tlIn.a
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tlIn.a <> arb.io.out
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}
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////////////////
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// Incoming Data Handling
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//Stage 1, Forward data from output node to the Idenity node of Coal and NonCoal
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// while setting the correct valid signal to base on if the request is Coalesced or not
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((outer.outputNode.in zip outer.outputNode.out) zip
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(outer.nonCoalNode.out zip outer.coalNode.out)).foreach{
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case( ((tlIn, _),(tlOut, _)), ((nonCoalOut, _),(coalOut, _)) ) =>
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tlIn.d <> tlOut.d
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nonCoalOut.d <> tlIn.d
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coalOut.d <> tlIn.d
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//rewrite valid signal
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nonCoalOut.d.valid := !isCoalReq(tlIn.d.bits.source) && tlIn.d.valid
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coalOut.d.valid := isCoalReq(tlIn.d.bits.source) && tlIn.d.valid
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}
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//Stage 2, Make both Idenity node Pass Through Channel D, for both Coal and NonCoal
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//
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((outer.nonCoalNode.out ++ outer.coalNode.out) zip
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(outer.nonCoalNode.in ++ outer.coalNode.in)).foreach{
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case ((tlOut,_),(tlIn,_)) =>
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tlIn.d <> tlOut.d
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}
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//Stage 3, Connect the channel D of nonCoalNodes to the perLane arbiters
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//Stage 3a, connect the noncoalesced edge to every single perlane arbiter
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val perLaneRespRRArbs = Seq.tabulate(config.numLanes){_=>
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Module(new RRArbiter(respNonCoalEntryT.cloneType, config.numArbiterOutputPorts))
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}
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outer.nonCoalNarrowNodes.zipWithIndex.foreach{
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case (node, node_idx) =>
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val (tlOut, edgeOut) = node.out(0)
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perLaneRespRRArbs.zipWithIndex.foreach{
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case(arb, arb_idx) =>
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val tlD2RespEntryFunc = tlD2respEntryFn()
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val perLaneArbTunnel = Module(new ConverterTunnel(
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tlOut.d.bits.cloneType,
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arb.io.in(0).bits.cloneType,
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tlD2RespEntryFunc
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)
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)
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perLaneArbTunnel.io.in <> tlOut.d
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arb.io.in(node_idx) <> perLaneArbTunnel.io.out
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//rewrite valid base on if source id actually belongs to this lane
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arb.io.in(node_idx).valid := belongsToLane(arb_idx.U, perLaneArbTunnel.io.out.bits.source) &&
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perLaneArbTunnel.io.out.valid
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}
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}
|
||||
//Stage 3b, connect coalesced request to
|
||||
val coalBundleRRArbiter = Module(new RRArbiter(respCoalBundleT.cloneType, config.numArbiterOutputPorts))
|
||||
//For the coalesced data response
|
||||
//Have an RR arbiter that holds the response data
|
||||
val coalRespRRArbiter = Module(new RRArbiter(
|
||||
outer.node.in(0)._1.d.bits.cloneType,
|
||||
config.numCoalReqs)
|
||||
)
|
||||
outer.coalReqNodes.zipWithIndex.foreach{
|
||||
case(node, node_idx) =>
|
||||
val (tlOut, edgeOut) = node.out(0)
|
||||
val tlD2CoalBundleFunc = tlD2CoalBundleFn()
|
||||
val coalBundleArbTunnel = Module(new ConverterTunnel(
|
||||
tlOut.d.bits.cloneType,
|
||||
coalBundleRRArbiter.io.in(0).bits.cloneType,
|
||||
tlD2CoalBundleFunc
|
||||
)
|
||||
)
|
||||
coalBundleArbTunnel.io.in <> tlOut.d
|
||||
coalBundleRRArbiter.io.in(node_idx) <> coalBundleArbTunnel.io.out
|
||||
case(node, idx) =>
|
||||
val (tlOut, edgeOut) = node.out(0)
|
||||
coalRespRRArbiter.io.in(idx) <> tlOut.d
|
||||
}
|
||||
|
||||
|
||||
//Connect 4, Connect the arbiters to output
|
||||
// connect the noncoalesced vector
|
||||
(perLaneRespRRArbs zip io.nonCoalResps).foreach{
|
||||
case (arb, resp) =>
|
||||
resp <> arb.io.out
|
||||
}
|
||||
// connect the coalesced bundle
|
||||
io.coalResp <> coalBundleRRArbiter.io.out
|
||||
|
||||
|
||||
|
||||
//Connect output of arbiter to coalesced reponse output
|
||||
io.coalResp.valid := coalRespRRArbiter.io.out.valid
|
||||
coalRespRRArbiter.io.out.ready := io.coalResp.ready
|
||||
val coalRespBundle = Wire(respCoalBundleT)
|
||||
coalRespBundle.fromTLD(coalRespRRArbiter.io.out.bits)
|
||||
io.coalResp.bits := coalRespBundle
|
||||
|
||||
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user