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  • 89c902c44f Bump vortex to upstream; fix addResource path accordingly Hansung Kim 2024-02-01 23:58:31 -08:00
  • 064f4f8541 Move EXTRA_SIM_PREPROC_DEFINES to mk fragment Hansung Kim 2024-02-01 23:56:38 -08:00
  • 6d2f89c6ae Remaining renames Hansung Kim 2024-02-05 09:44:55 -08:00
  • 3224019114 Rename VortexTile -> RadianceTile Hansung Kim 2024-02-01 17:27:18 -08:00
  • 9b0aa387c3 Merge branch 'main' of https://github.com/ucb-bar/radiance into main Richard Yan 2024-02-02 15:55:17 -08:00
  • f3cee5abff enable gpu to use separate physical memory range Richard Yan 2024-02-02 15:55:02 -08:00
  • 2fcb1f374f Rename to RadianceTile.scala Hansung Kim 2024-02-01 14:42:43 -08:00
  • 20191a9253 Merge branch 'main' of https://github.com/hansungk/radiance into main Richard Yan 2024-01-31 13:13:55 -08:00
  • e20799a7e1 make shared memory use external spad Richard Yan 2024-01-31 13:12:07 -08:00
  • 2aab555f0a Connect unified_mem_node from Gemmini Hansung Kim 2024-01-30 18:01:32 -08:00
  • a648b388ef Bump radpie Hansung Kim 2024-01-30 18:01:19 -08:00
  • dc86d69da4 Add make fragment Hansung Kim 2024-01-29 15:40:15 -08:00
  • 2c7d8650d4 Bump radpie Hansung Kim 2024-01-29 13:58:34 -08:00
  • 149f8b193e Add memfuzzer DPI library as submodule Hansung Kim 2024-01-29 13:18:58 -08:00
  • 16c4292e57 Rename core.io.cease to finished; bump vortex Hansung Kim 2024-01-26 14:25:12 -08:00
  • cfce029b70 Generate explicit clock domain in CanHaveMemtraceCore Hansung Kim 2024-01-26 00:13:14 -08:00
  • 78075e5148 Bump vortex Hansung Kim 2024-01-25 23:24:05 -08:00
  • df26764fc0 Reduce sharedmem addr mapping to 8KB Hansung Kim 2024-01-23 22:14:15 -08:00
  • 17553ccfcd Connect stlNode of Gemmini Hansung Kim 2024-01-23 18:58:03 -08:00
  • 2e5f6d8427 Support RoCC instantiation in VortexTile Hansung Kim 2024-01-23 16:24:55 -08:00
  • d2032b563c Don't set XLen in WithRadianceCores Hansung Kim 2024-01-23 16:11:32 -08:00
  • 34fce0e34d Commented out TLRAMCoalescerFuzzer test module Hansung Kim 2024-01-23 13:47:22 -08:00
  • 164e722790 Pass inflight to DPI to determine proper fuzz termination Hansung Kim 2024-01-23 01:10:59 -08:00
  • f26c9dfb11 Put pipereg between uncoalescer output and respQueue Hansung Kim 2024-01-22 16:51:35 -08:00
  • 75d51e3d1d Distinguish time-coalescing window from request queue depth Hansung Kim 2024-01-22 14:39:34 -08:00
  • b2a83c788e Pass both A and D bundles to memfuzzer DPI Hansung Kim 2024-01-22 01:54:45 -08:00
  • e7340ba840 Use negedge for DPI calls to avoid confusion Hansung Kim 2024-01-22 01:47:39 -08:00
  • a499dfff32 Enable conditional instantiation of coalescer in FuzzerTile Hansung Kim 2024-01-22 01:43:09 -08:00
  • 80414964f0 Remove unnecessary id.bits from SourceGenerator table row Hansung Kim 2024-01-22 01:41:24 -08:00
  • ec02a12220 Use DecoupledIO instead of explicit valid in TraceLine bundle Hansung Kim 2024-01-21 17:50:00 -08:00
  • d56981a0b1 Fix io.finished of MemTraceDriver not waiting for inflight responses Hansung Kim 2024-01-21 15:33:15 -08:00
  • e183606193 Write basic DPI mem fuzzer Hansung Kim 2024-01-20 21:46:14 -08:00
  • 6ff127eb51 Write faux memory fuzzer Hansung Kim 2024-01-19 22:37:29 -08:00
  • 9e7a8f4ef2 Add FuzzerTile Hansung Kim 2024-01-19 22:05:21 -08:00
  • 69bf554d0f Split SimMem verilog constants to a .vh file Hansung Kim 2024-01-19 18:25:03 -08:00
  • 40ec2a276b Remove unittest configs carried over from rocket-chip Hansung Kim 2024-01-19 18:24:22 -08:00
  • ceb7ee79fe Don't gitignore *.v Hansung Kim 2024-01-19 16:09:41 -08:00
  • 737f24fd77 scalafmt Hansung Kim 2024-01-19 15:16:37 -08:00
  • fec3d61dd6 Decrease imemSourceWidth to 4 Hansung Kim 2024-01-18 22:16:22 -08:00
  • 0fd4d0a76f Split IO for lookup and dealloc in InflightTable Hansung Kim 2024-01-18 22:02:06 -08:00
  • 9ae1d9c392 Put a pipeline stage at uncoalescer Hansung Kim 2024-01-18 21:31:23 -08:00
  • 7e906a39fb Reduce default respQueueDepth to 2 Hansung Kim 2024-01-18 19:22:59 -08:00
  • 95dcecbe03 Fix uncoalesced response being dropped Hansung Kim 2024-01-18 18:50:43 -08:00
  • b1a37d0dda Streamline upstream flow with regards to CoalSourceGen Hansung Kim 2024-01-18 18:15:18 -08:00
  • 086b2a5398 Clean up uncoalescer -> respQueue doc Hansung Kim 2024-01-18 18:12:49 -08:00
  • 46f5e8b920 Disable force assert for RespQueue block Hansung Kim 2024-01-18 18:10:33 -08:00
  • 2b8ef4cb30 Create coalResp backpressure when response queues are full Hansung Kim 2024-01-18 01:09:28 -08:00
  • eeb92da8a1 Fix InFlightTable lookup assert Hansung Kim 2024-01-18 01:07:49 -08:00
  • e96836c190 Fix inflightCounter debug counter Hansung Kim 2024-01-18 01:06:28 -08:00
  • 138e83b68a Assert coreWriteReqQueue is never full in VortexCache Hansung Kim 2024-01-18 01:05:23 -08:00
  • e53c3fed9b add back purged files Richard Yan 2024-01-17 16:40:13 -08:00
  • 7914607304 Bump vortex with IBUF/LSUQ size change Hansung Kim 2024-01-16 23:54:39 -08:00
  • 37d2af5478 Reflect upstream rocket-chip changes Hansung Kim 2024-01-16 23:20:32 -08:00
  • cd1022c608 Remove use of HasTiles to reflect upstream change Hansung Kim 2024-01-16 22:59:56 -08:00
  • 132742ea88 Distinguish LSU lanes from SIMD lanes and elaborate tag width logic Hansung Kim 2024-01-16 22:20:16 -08:00
  • 263f00baed Merge remote-tracking branch 'origin/vortex2' into restructure Richard Yan 2024-01-16 17:49:41 -08:00
  • dea005a179 incorporate vortex2 Richard Yan 2024-01-16 17:41:33 -08:00
  • f9b7e9fbe4 restructure from rocket-chip to radiance Richard Yan 2024-01-16 16:21:50 -08:00
  • c742a13c1e restructure: initial filter pass Richard Yan 2024-01-11 10:08:43 -08:00
  • 9e1ddfaeb9 Bump vortex with IO flattening Hansung Kim 2024-01-04 01:35:30 -08:00
  • 51e17e709b Flatten smem bundle of Vortex core IO into 1-D arrays Hansung Kim 2024-01-04 00:53:18 -08:00
  • 60cd72a9d6 Flatten dmem bundle of Vortex core IO into 1-D arrays Hansung Kim 2024-01-04 00:17:00 -08:00
  • 773cfcbd6e Bump vortex for external smem Hansung Kim 2024-01-01 14:27:37 -08:00
  • 8c12c7af16 Instantiate multiple TLRAMs as sharedmem banks Hansung Kim 2024-01-01 12:49:23 -08:00
  • 95e05f5457 Connect smem core IO to TL with translation Hansung Kim 2024-01-01 02:24:57 -08:00
  • 15c3c55cb6 Make empty sharedmem diplomacy nodes Hansung Kim 2024-01-01 00:46:01 -08:00
  • cb2bc8cc0a Rename VortexBank -> VortexCache Hansung Kim 2024-01-01 00:08:25 -08:00
  • 65446946be Bump vortex Hansung Kim 2023-12-10 05:58:21 -08:00
  • efac9b7d0b Better logic for {imem,dmem}TagWidth Hansung Kim 2023-12-10 05:58:00 -08:00
  • ca57c8d6a3 TLFragmenter bug fix Zekai Lin 2023-12-09 20:27:13 -08:00
  • 2879108804 Accept coalescer enable at WithCoalescer config Hansung Kim 2023-12-01 19:01:06 -08:00
  • 4eb9973b2c Attempt to replicate bitwidth logic for dmem/imem tag Hansung Kim 2023-11-29 15:13:17 -08:00
  • 2bdaf3a0a8 Fix undefined {MEM,WORD}_ADDR_SIZE Hansung Kim 2023-11-28 22:49:48 -08:00
  • 0589b310f1 Add missing parameters for VX_cache_top Hansung Kim 2023-11-28 20:32:49 -08:00
  • 6248926b47 Remove icache-specific address set and naming Hansung Kim 2023-11-28 20:08:46 -08:00
  • 74fe530105 Enable configuring MSHR size from Chisel Hansung Kim 2023-11-28 19:55:08 -08:00
  • f8d7169d19 Delete old addResource for vortex v1 Hansung Kim 2023-11-28 19:44:02 -08:00
  • 4f274af363 Bump vortex with way_idx revert Hansung Kim 2023-11-28 19:34:32 -08:00
  • 4efe9cb93f Instantiate separate VortexL1Cache for imem and dmem Hansung Kim 2023-11-28 19:22:11 -08:00
  • 0d60180d0d Change NUM_WAYS from 1 to 4 Hansung Kim 2023-11-28 18:43:25 -08:00
  • d45cf835cf Remove dedicated icache bank from VortexBank Hansung Kim 2023-11-28 18:42:58 -08:00
  • b66be6c3ae Respect VX_cache's MEM_TAG_WIDTH; rename coalToVxCacheNode Hansung Kim 2023-11-28 16:53:41 -08:00
  • c5e37dd3b8 Rename l2ReqSourceGenSize -> memSideSourceIds Hansung Kim 2023-11-28 14:55:52 -08:00
  • bd1aaaccfe Bump vortex with trace and CSR fix Hansung Kim 2023-11-28 12:52:23 -08:00
  • f187291a9c VortexBank: Update addResource for vortex2; WIP fix params Hansung Kim 2023-11-28 12:51:34 -08:00
  • 8ed82e8261 Remove unclear size width requirement in tl adapter Hansung Kim 2023-11-27 16:42:07 -08:00
  • dafacf9873 Bump vortex Hansung Kim 2023-11-19 17:55:23 -08:00
  • ccd6582991 Set correct mask for PutPartial for core writes Hansung Kim 2023-11-19 17:54:08 -08:00
  • d7cbf4916a Rename sourceWidth -> tagWidth Hansung Kim 2023-11-19 17:49:47 -08:00
  • 1346f74210 Bump vortex with tag width fix Hansung Kim 2023-11-17 19:13:48 -08:00
  • 765c8ef1b0 Remove unnecessary write ack filtering logic in VortexTLAdapter Hansung Kim 2023-11-17 19:12:35 -08:00
  • 6802d23598 Change dcache sourceWidth constant to match DCACHE_NOSM_TAG_WIDTH Hansung Kim 2023-11-17 19:12:03 -08:00
  • 05ffa884a6 Bump vortex with DCR fix Hansung Kim 2023-11-16 18:00:56 -08:00
  • 65f4264d57 Pass hang100 address to wrapper verilog Hansung Kim 2023-11-16 18:00:40 -08:00
  • dca74eface Bump vortex to 2.0 Hansung Kim 2023-11-15 22:06:17 -08:00
  • 134dd4eb59 Update BlackBox to include Vortex 2.0 Hansung Kim 2023-11-15 21:58:40 -08:00
  • 0768a7abc9 More cleanup and doc Hansung Kim 2023-11-10 18:49:11 -08:00
  • 0bb8e6d705 Bump vortex with ibuffer size fix Hansung Kim 2023-11-10 18:38:59 -08:00
  • ecfa18ce69 Rename to VortexBank Hansung Kim 2023-11-10 17:46:04 -08:00
  • 78e09160a2 Rename L1System -> VortexL1; do not expose bank Xbar from L1 Hansung Kim 2023-11-10 16:11:43 -08:00