De-duplicate equivalent Request bundles using NonCoal/Coal variants
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@@ -165,6 +165,16 @@ class Request(sourceWidth: Int, sizeWidth: Int, addressWidth: Int, dataWidth: In
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bits
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}
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}
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class NonCoalescedRequest(config: CoalescerConfig)
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extends Request(sourceWidth = log2Ceil(config.numOldSrcIds),
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sizeWidth = config.wordSizeWidth,
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addressWidth = config.addressWidth,
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dataWidth = config.wordSizeInBytes * 8)
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class CoalescedRequest(config: CoalescerConfig)
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extends Request(sourceWidth = log2Ceil(config.numNewSrcIds),
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sizeWidth = log2Ceil(config.maxCoalLogSize),
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addressWidth = config.addressWidth,
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dataWidth = (8 * (1 << config.maxCoalLogSize)))
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class Response(sourceWidth: Int, sizeWidth: Int, dataWidth: Int) extends Bundle {
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val op = UInt(1.W) // 0=READ 1=WRITE
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@@ -194,7 +204,6 @@ class Response(sourceWidth: Int, sizeWidth: Int, dataWidth: Int) extends Bundle
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this.error := bundle.denied
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}
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}
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class NonCoalescedResponse(config: CoalescerConfig)
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extends Response(sourceWidth = log2Ceil(config.numOldSrcIds),
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sizeWidth = config.wordSizeWidth,
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@@ -352,7 +361,7 @@ class CoalShiftQueue[T <: Data](gen: T, entries: Int, config: CoalescerConfig) e
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}
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// Software model: coalescer.py
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class MonoCoalescer(coalLogSize: Int, windowT: CoalShiftQueue[Request],
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class MonoCoalescer(coalLogSize: Int, windowT: CoalShiftQueue[NonCoalescedRequest],
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config: CoalescerConfig) extends Module {
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val io = IO(new Bundle {
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val window = Input(windowT.io.cloneType)
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@@ -483,7 +492,7 @@ class MonoCoalescer(coalLogSize: Int, windowT: CoalShiftQueue[Request],
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// coalesced request out of all possible combinations.
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//
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// Software model: coalescer.py
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class MultiCoalescer(windowT: CoalShiftQueue[Request], coalReqT: Request,
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class MultiCoalescer(windowT: CoalShiftQueue[NonCoalescedRequest], coalReqT: Request,
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config: CoalescerConfig) extends Module {
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val io = IO(new Bundle {
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// coalescing window, connected to the contents of the request queues
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@@ -622,14 +631,12 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
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s"TL param addressBits (${outer.cpuNode.in.head._1.params.addressBits}) " +
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s"mismatch with config.addressWidth (${config.addressWidth})")
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val sourceWidth = outer.cpuNode.in.head._1.params.sourceBits
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val oldSourceWidth = outer.cpuNode.in.head._1.params.sourceBits
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// note we are using word size. assuming all coalescer inputs are word sized
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val reqQueueEntryT = new Request(sourceWidth, config.wordSizeWidth,
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config.addressWidth, (config.wordSizeInBytes * 8))
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val reqQueueEntryT = new NonCoalescedRequest(config)
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val reqQueues = Module(new CoalShiftQueue(reqQueueEntryT, config.queueDepth, config))
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val coalReqT = new Request(log2Ceil(config.numNewSrcIds), log2Ceil(config.maxCoalLogSize),
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config.addressWidth, (1 << config.maxCoalLogSize) * 8)
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val coalReqT = new CoalescedRequest(config)
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val coalescer = Module(new MultiCoalescer(reqQueues, coalReqT, config))
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coalescer.io.window := reqQueues.io
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reqQueues.io.coalescable := coalescer.io.coalescable
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@@ -716,7 +723,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
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val numPerLaneReqs = config.queueDepth
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// FIXME: no need to contain maxCoalLogSize data
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val respQueueEntryT = new Response(sourceWidth, log2Ceil(config.maxCoalLogSize),
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val respQueueEntryT = new Response(oldSourceWidth, log2Ceil(config.maxCoalLogSize),
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(1 << config.maxCoalLogSize) * 8)
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val respQueues = Seq.tabulate(config.numLanes) { _ =>
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Module(
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@@ -1846,21 +1853,10 @@ class CoalescerXbar(config: CoalescerConfig) (implicit p: Parameters) extends La
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val node = TLIdentityNode()
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node :=* outputXbar.node
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val nonCoalEntryT = new Request(
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log2Ceil(config.numOldSrcIds),
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config.wordSizeWidth,
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config.addressWidth,
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config.wordSizeInBytes * 8
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)
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val coalEntryT = new Request(
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log2Ceil(config.numOldSrcIds),
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log2Ceil(config.maxCoalLogSize),
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config.addressWidth,
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(1 << config.maxCoalLogSize) * 8
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)
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val nonCoalEntryT = new NonCoalescedRequest(config)
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val coalEntryT = new CoalescedRequest(config)
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val respNonCoalEntryT = new NonCoalescedResponse(config)
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val respCoalBundleT = new CoalescedResponse(config)
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lazy val module = new CoalescerXbarImpl(
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this, config, nonCoalEntryT, coalEntryT, respNonCoalEntryT, respCoalBundleT)
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@@ -127,12 +127,12 @@ class DummyCoalescingUnitTBImp(outer: DummyCoalescingUnitTB) extends LazyModuleI
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)
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val reqQueueEnqReady = peekIn(0).asInstanceOf[Seq[Bool]].map(x => IO(x.cloneType))
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val reqQueueEnqBits = peekIn(1).asInstanceOf[Seq[ReqQueueEntry]].map(x => IO(x.cloneType))
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val reqQueueEnqBits = peekIn(1).asInstanceOf[Seq[Request]].map(x => IO(x.cloneType))
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val reqQueueEnqValid = peekIn(2).asInstanceOf[Seq[Bool]].map(x => IO(x.cloneType))
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val reqQueueDeqBits = peekIn(3).asInstanceOf[Seq[ReqQueueEntry]].map(x => IO(Output(x.cloneType)))
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val reqQueueDeqBits = peekIn(3).asInstanceOf[Seq[Request]].map(x => IO(Output(x.cloneType)))
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val reqQueueDeqValid = peekIn(4).asInstanceOf[Seq[Bool]].map(x => IO(Output(x.cloneType)))
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val coalReqReady = IO(Output(peekIn(5).asInstanceOf[Bool].cloneType))
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val coalReqBits = IO(Output(peekIn(6).asInstanceOf[ReqQueueEntry].cloneType))
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val coalReqBits = IO(Output(peekIn(6).asInstanceOf[Request].cloneType))
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val coalReqValid = IO(Output(peekIn(7).asInstanceOf[Bool].cloneType))
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val coalInvalidate = IO(Output(peekIn(8).asInstanceOf[Valid[Vec[UInt]]].cloneType))
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