CoalArbiter RTL implementation first draft, verification WIP
This commit is contained in:
Vamber Yang
@@ -810,6 +810,12 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
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class CoalescedResponseBundle(config: CoalescerConfig) extends Bundle {
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val source = UInt(log2Ceil(config.numNewSrcIds).W)
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val data = UInt((8 * (1 << config.maxCoalLogSize)).W)
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def fromTLD(bundle:TLBundleD): Unit = {
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this.source := bundle.source
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this.data := bundle.data
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}
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}
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class Uncoalescer(config: CoalescerConfig) extends Module {
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@@ -1766,12 +1772,20 @@ class CoalArbiter(config: CoalescerConfig) (implicit p: Parameters) extends Lazy
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coalNode := coalReqNode
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)
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//Assertion Section
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def isPowerOfTwo(n: Int): Boolean = {
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(n > 0) && ((n & (n - 1)) == 0)
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}
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assert(isPowerOfTwo(config.numOldSrcIds), "Number of old source id must be power of 2")
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assert(isPowerOfTwo(config.numNewSrcIds), "Number of new source id must be power of 2")
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//Below is for efficient conversion from Global to Local bits
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//Also, we should have more source id for coalesced request for better perf
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assert(config.numNewSrcIds >= config.numOldSrcIds, "new source id must be equal or greater than old source id")
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// 1 Final Output Identity Node
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val outputNode = TLIdentityNode()
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//Explictly define I/O bundule tyoe
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val nonCoalEntryT = new ReqQueueEntry(
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log2Ceil(config.numOldSrcIds),
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config.wordWidth,
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@@ -1791,10 +1805,13 @@ class CoalArbiter(config: CoalescerConfig) (implicit p: Parameters) extends Lazy
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)
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val respCoalBundleT = new CoalescedResponseBundle(config)
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lazy val module = new CoalArbiterImpl(
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this, config, nonCoalEntryT, coalEntryT, respNonCoalEntryT, respCoalBundleT)
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}
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class CoalArbiterImpl(outer: CoalArbiter,
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@@ -1816,7 +1833,7 @@ class CoalArbiterImpl(outer: CoalArbiter,
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//Helper Class & Method Section
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//Provide an decoupled interface between bundle of 2 different type
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//Provide an simple decoupled interface between bundle of 2 different type
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class ConverterTunnel[T <: Data, U <: Data](
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genA: T,
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genB: U,
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@@ -1833,19 +1850,36 @@ class CoalArbiterImpl(outer: CoalArbiter,
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def canHitBank(addr: UInt, bankNum: UInt) : Bool = {
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val byteOffset = 3
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val bankBase = log2Ceil(config.bankStrideInBytes)
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val bankOffset = log2Ceil(config.numArbiterOutputPorts)
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(addr(bankBase+bankOffset-byteOffset, bankBase - byteOffset) === bankNum)
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val byteOffset = 3
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val bankBase = log2Ceil(config.bankStrideInBytes)
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val bankOffset = log2Ceil(config.numArbiterOutputPorts)
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(addr(bankBase+bankOffset-byteOffset, bankBase - byteOffset) === bankNum)
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}
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//This Operation Could be Expensive
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def toGlobalSourceId(isCoalReq : Bool, laneIndex : UInt, sourceID : UInt) : UInt = {
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val res = Mux(isCoalReq,
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config.numNewSrcIds.U * laneIndex + sourceID,
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config.numOldSrcIds.U * laneIndex + sourceID + config.numNewSrcIds.U * config.numCoalReqs.U
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)
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res
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def toGlobalSourceId(isCoalReq : Bool, laneIdx : UInt, sourceID : UInt) : UInt = {
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val gid = Mux(isCoalReq,
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config.numNewSrcIds.U * laneIdx + sourceID,
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config.numOldSrcIds.U * laneIdx + sourceID + config.numNewSrcIds.U * config.numCoalReqs.U
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)
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gid
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}
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//All the ids are power of 2, so we can just look at bottom bits
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def toLocalSourceId(isCoalReq : Bool, sourceID : UInt) : UInt = {
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val sid = Mux(isCoalReq,
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sourceID(log2Ceil(config.numNewSrcIds)-1, 0),
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sourceID(log2Ceil(config.numOldSrcIds)-1, 0)
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)
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sid
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}
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def belongsToLane(laneIdx: UInt, gid: UInt) : Bool = {
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val base = config.numNewSrcIds.U * config.numCoalReqs.U
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((gid >= base + config.numOldSrcIds.U * laneIdx) &&
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(gid < base + config.numOldSrcIds.U * (laneIdx+1.U)))
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}
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def isCoalReq(gid : UInt) : Bool = {
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gid <= config.numNewSrcIds.U * config.numCoalReqs.U
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}
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//
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@@ -1858,26 +1892,52 @@ class CoalArbiterImpl(outer: CoalArbiter,
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config.addressWidth,
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log2Ceil(config.wordSizeInBytes)
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)
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// Before a nonCoalesced request enter RR arbiter
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val coalGiDEntryT = new ReqQueueEntry(
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log2Ceil(fullSourceIdRange),
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log2Ceil(config.maxCoalLogSize),
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config.addressWidth,
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config.maxCoalLogSize //already log 2
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)
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// Before either a coalesced or non coalesced request enter RR arbiter
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// It needs to turn its source into global source id
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// Unfortunately this involves extending the width of sourceid field, and a new bundle must be created
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// This is a higher order function
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def nonCoal2gidReqFn(laneIndex : UInt)
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: ReqQueueEntry => ReqQueueEntry = {
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def func(lid_req : ReqQueueEntry) : ReqQueueEntry = {
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val gid_req = nonCoalGiDEntryT.cloneType
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gid_req <> lid_req
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gid_req.source := toGlobalSourceId(false.B, laneIndex, lid_req.source)
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gid_req
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}
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func
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def reqEntry2GidReqFn(laneIndex : UInt, reqEntryT : ReqQueueEntry, isCoalReq : Bool) : ReqQueueEntry => ReqQueueEntry = {
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def func(lid_req : ReqQueueEntry) : ReqQueueEntry = {
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val gid_req = reqEntryT.cloneType
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gid_req <> lid_req
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gid_req.source := toGlobalSourceId(isCoalReq, laneIndex, lid_req.source)
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gid_req
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}
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func
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}
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def nonCoal2TLAFn(edgeOut: TLEdgeOut) : ReqQueueEntry => TLBundleA = {
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def func(gid_req : ReqQueueEntry) : TLBundleA = {
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gid_req.toTLA(edgeOut)
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}
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func
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def reqEntry2TLAFn(edgeOut: TLEdgeOut) : ReqQueueEntry => TLBundleA = {
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def func(gid_req : ReqQueueEntry) : TLBundleA = {
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gid_req.toTLA(edgeOut)
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}
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func
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}
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def tlD2respEntryFn() : TLBundleD => RespQueueEntry = {
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def func(bundle: TLBundleD) : RespQueueEntry = {
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val resp = Wire(respNonCoalEntryT)
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resp.fromTLD(bundle)
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resp.source := toLocalSourceId(false.B, bundle.source)
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resp
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}
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func
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}
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def tlD2CoalBundleFn() : TLBundleD => CoalescedResponseBundle = {
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def func(bundle: TLBundleD) : CoalescedResponseBundle = {
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val coalbundle = Wire(respCoalBundleT)
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coalbundle.fromTLD(bundle)
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coalbundle.source := toLocalSourceId(true.B, bundle.source)
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coalbundle
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}
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func
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}
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/////////////////////////////////////////////////////
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@@ -1899,47 +1959,80 @@ class CoalArbiterImpl(outer: CoalArbiter,
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case (req, q) => q.io.enq <> req
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}
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//Stage 1b: connect output of Queues to the RR arbiters (each arbiter is for a unique bank)
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// the two loops below could be merged into one loop, but separated for readability
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val nonCoalRRArbiters = Seq.tabulate(config.numArbiterOutputPorts){_=>
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Module(new RRArbiter(nonCoalGiDEntryT.cloneType, config.numLanes))
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}
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nonCoalReqsQueues.zipWithIndex.foreach{ case(q, q_idx) =>
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nonCoalRRArbiters.zipWithIndex.foreach{ case(arb, arb_idx) =>
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val nonCoal2gidFunc = nonCoal2gidReqFn(q_idx.U)
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val nonCoal2gidFunc = reqEntry2GidReqFn(q_idx.U, nonCoalGiDEntryT, false.B)
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val nonCoalRRArbTunnel = Module(new ConverterTunnel(
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coalEntryT.cloneType,
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nonCoalEntryT.cloneType,
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nonCoalGiDEntryT.cloneType,
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nonCoal2gidFunc)
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)
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nonCoalRRArbTunnel.io.in <> q.io.deq
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arb.io.in(q_idx) <> nonCoalRRArbTunnel.io.out
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//OverWrite Valid base on if we can actually hit this bank
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arb.io.in(q_idx).valid := canHitBank(nonCoalRRArbTunnel.io.out.bits.address, arb_idx.U)
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arb.io.in(q_idx).valid := canHitBank(nonCoalRRArbTunnel.io.out.bits.address, arb_idx.U) &&
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nonCoalRRArbTunnel.io.out.valid
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}
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}
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val coalRRArbiters = Seq.tabulate(config.numArbiterOutputPorts){_=>
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Module(new RRArbiter(coalGiDEntryT.cloneType, config.numCoalReqs))
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}
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coalReqsQueues.zipWithIndex.foreach{ case(q, q_idx) =>
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coalRRArbiters.zipWithIndex.foreach{ case(arb, arb_idx) =>
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val coal2gidFunc = reqEntry2GidReqFn(q_idx.U, coalGiDEntryT, true.B)
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val coalRRArbTunnel = Module(new ConverterTunnel(
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coalEntryT.cloneType,
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coalGiDEntryT.cloneType,
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coal2gidFunc)
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)
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coalRRArbTunnel.io.in <> q.io.deq
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arb.io.in(q_idx) <> coalRRArbTunnel.io.out
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//OverWrite Valid
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arb.io.in(q_idx).valid := canHitBank(coalRRArbTunnel.io.out.bits.address, arb_idx.U) &&
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coalRRArbTunnel.io.out.valid
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}
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}
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//Stage 2, Connect the output of Arbiters to respective nonCoal node
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//Stage 2a, the K Arbiters for Coalesced
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(outer.nonCoalNarrowNodes zip nonCoalRRArbiters).foreach{
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case (node, arb) =>
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val (tlOut, edgeOut) = node.out(0)
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val coal2TLAFunc = nonCoal2TLAFn(edgeOut)
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val nonCoalTLATunnel = Module(new ConverterTunnel(
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arb.io.out.bits.cloneType,
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tlOut.a.bits.cloneType,
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coal2TLAFunc
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// Concatenate the nodes , concatenates the arbiters, and zip them together, then loop
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// the reqEntry2TLA will generate different TLA bundle depending on if the Req is coal or non coal
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((outer.nonCoalNarrowNodes++outer.coalReqNodes) zip
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(nonCoalRRArbiters++coalRRArbiters)).foreach{
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case (node, arb) =>
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val (tlOut, edgeOut) = node.out(0)
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val coal2TLAFunc = reqEntry2TLAFn(edgeOut)
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val nonCoalTLATunnel = Module(new ConverterTunnel(
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arb.io.out.bits.cloneType,
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tlOut.a.bits.cloneType,
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coal2TLAFunc
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)
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)
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)
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nonCoalTLATunnel.io.in <> arb.io.out
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tlOut.a <> nonCoalTLATunnel.io.out
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nonCoalTLATunnel.io.in <> arb.io.out
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tlOut.a <> nonCoalTLATunnel.io.out
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}
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//Stage 3, Connect the K edges Identity Node to PO arbiter
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// noncoalesced to port 1, coalesced to por1
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//Stage 3, Make the Idenity node pass through channel A
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// Connect the K edges Identity Node to PO arbiter
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// noncoalesced to port 1, coalesced to port 0
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val priorityArbs = Seq.tabulate(config.numArbiterOutputPorts){_=>
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Module(new Arbiter(outer.outputNode.out(0)._1.a.bits.cloneType, 2))
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}
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//Make both Idenity node Pass Through Channel A, for both Coal and NonCoal
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((outer.nonCoalNode.out ++ outer.coalNode.out) zip
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(outer.nonCoalNode.in ++ outer.coalNode.in)).foreach{
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case ((tlOut,_),(tlIn,_)) =>
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tlOut.a <> tlIn.a
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}
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//Connection to PO Arbiters
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((outer.nonCoalNode.out zip outer.coalNode.out) zip priorityArbs).foreach{
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case (((nonCoalOut, _),(coalOut, _)), arb) =>
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arb.io.in(1) <> nonCoalOut.a
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@@ -1951,10 +2044,92 @@ class CoalArbiterImpl(outer: CoalArbiter,
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//And make idenitity node passs through the inputs
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((outer.outputNode.in zip outer.outputNode.out) zip priorityArbs).foreach{
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case (((tlIn, _), (tlOut, _)), arb) =>
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tlOut <> tlIn
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tlOut.a <> tlIn.a
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tlIn.a <> arb.io.out
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}
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////////////////
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// Incoming Data Handling
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//Stage 1, Forward data from output node to the Idenity node of Coal and NonCoal
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// while setting the correct valid signal to base on if the request is Coalesced or not
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((outer.outputNode.in zip outer.outputNode.out) zip
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(outer.nonCoalNode.out zip outer.coalNode.out)).foreach{
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case( ((tlIn, _),(tlOut, _)), ((nonCoalOut, _),(coalOut, _)) ) =>
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tlIn.d <> tlOut.d
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nonCoalOut.d <> tlIn.d
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coalOut.d <> tlIn.d
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//rewrite valid signal
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nonCoalOut.d.valid := !isCoalReq(tlIn.d.bits.source) && tlIn.d.valid
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coalOut.d.valid := isCoalReq(tlIn.d.bits.source) && tlIn.d.valid
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}
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//Stage 2, Make both Idenity node Pass Through Channel D, for both Coal and NonCoal
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//
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((outer.nonCoalNode.out ++ outer.coalNode.out) zip
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(outer.nonCoalNode.in ++ outer.coalNode.in)).foreach{
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case ((tlOut,_),(tlIn,_)) =>
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tlIn.d <> tlOut.d
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}
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//Stage 3, Connect the channel D of nonCoalNodes to the perLane arbiters
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//Stage 3a, connect the noncoalesced edge to every single perlane arbiter
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val perLaneRespRRArbs = Seq.tabulate(config.numLanes){_=>
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Module(new RRArbiter(respNonCoalEntryT.cloneType, config.numArbiterOutputPorts))
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}
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outer.nonCoalNarrowNodes.zipWithIndex.foreach{
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case (node, node_idx) =>
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val (tlOut, edgeOut) = node.out(0)
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perLaneRespRRArbs.zipWithIndex.foreach{
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case(arb, arb_idx) =>
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val tlD2RespEntryFunc = tlD2respEntryFn()
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val perLaneArbTunnel = Module(new ConverterTunnel(
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tlOut.d.bits.cloneType,
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arb.io.in(0).bits.cloneType,
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tlD2RespEntryFunc
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)
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)
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perLaneArbTunnel.io.in <> tlOut.d
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arb.io.in(node_idx) <> perLaneArbTunnel.io.out
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//rewrite valid base on if source id actually belongs to this lane
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arb.io.in(node_idx).valid := belongsToLane(arb_idx.U, perLaneArbTunnel.io.out.bits.source) &&
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perLaneArbTunnel.io.out.valid
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}
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}
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//Stage 3b, connect coalesced request to
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val coalBundleRRArbiter = Module(new RRArbiter(respCoalBundleT.cloneType, config.numArbiterOutputPorts))
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outer.coalReqNodes.zipWithIndex.foreach{
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case(node, node_idx) =>
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val (tlOut, edgeOut) = node.out(0)
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val tlD2CoalBundleFunc = tlD2CoalBundleFn()
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val coalBundleArbTunnel = Module(new ConverterTunnel(
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tlOut.d.bits.cloneType,
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coalBundleRRArbiter.io.in(0).bits.cloneType,
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tlD2CoalBundleFunc
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)
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)
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coalBundleArbTunnel.io.in <> tlOut.d
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coalBundleRRArbiter.io.in(node_idx) <> coalBundleArbTunnel.io.out
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}
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//Connect 4, Connect the arbiters to output
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// connect the noncoalesced vector
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(perLaneRespRRArbs zip io.nonCoalResps).foreach{
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case (arb, resp) =>
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resp <> arb.io.out
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}
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// connect the coalesced bundle
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io.coalResp <> coalBundleRRArbiter.io.out
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}
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