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Set up proper Config system for numLanes

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TODO: tracefilename should not really be inside SIMTCoreParam.
This commit is contained in:
Hansung Kim
2023-05-08 17:32:31 -07:00
parent 25c0b6cfa5
commit f6be54a122
2 changed files with 25 additions and 38 deletions
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18
src/main/scala/tilelink/Coalescing.scala
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@@ -5,12 +5,17 @@ package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.ChiselEnum
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.diplomacy._
// import freechips.rocketchip.devices.tilelink.TLTestRAM
import freechips.rocketchip.util.MultiPortQueue
import freechips.rocketchip.unittest._
// TODO: find better place for these
case class SIMTCoreParams(nLanes: Int = 4, tracefilename: String = "undefined")
case object SIMTCoreKey extends Field[Option[SIMTCoreParams]](None)
trait InFlightTableSizeEnum extends ChiselEnum {
val INVALID: Type
val FOUR: Type
@@ -1635,14 +1640,15 @@ class DummyCoalescerTest(timeout: Int = 500000)(implicit p: Parameters)
// tracedriver --> coalescer --> tracelogger --> tlram
class TLRAMCoalescerLogger(filename: String)(implicit p: Parameters) extends LazyModule {
// TODO: use parameters for numLanes
val numLanes = defaultConfig.numLanes
val numLanes = p(SIMTCoreKey).get.nLanes
println(s"============ numLanes: ${numLanes}")
val config = defaultConfig.copy(numLanes = numLanes)
val driver = LazyModule(new MemTraceDriver(defaultConfig, filename))
val driver = LazyModule(new MemTraceDriver(config, filename))
val coreSideLogger = LazyModule(
new MemTraceLogger(numLanes, filename, loggerName = "coreside")
)
val coal = LazyModule(new CoalescingUnit(defaultConfig))
val coal = LazyModule(new CoalescingUnit(config))
val memSideLogger = LazyModule(new MemTraceLogger(numLanes + 1, filename, loggerName = "memside"))
val rams = Seq.fill(numLanes + 1)( // +1 for coalesced edge
LazyModule(
@@ -1650,7 +1656,7 @@ class TLRAMCoalescerLogger(filename: String)(implicit p: Parameters) extends Laz
// edges globally, by way of Diplomacy communicating the TL slave
// parameters to the upstream nodes.
new TLRAM(address = AddressSet(0x0000, 0xffffff),
beatBytes = (1 << defaultConfig.dataBusWidth))
beatBytes = (1 << config.dataBusWidth))
)
)

45
src/main/scala/tilelink/TracerSystemMem.scala
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@@ -1,44 +1,25 @@
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes}
import org.chipsalliance.cde.config.{Parameters, Field, Config}
import freechips.rocketchip.subsystem.{BaseSubsystem}
import org.chipsalliance.cde.config.{Parameters, Config}
// class class, consumed by WithGPUTacer config and GPUTracerKey
case class GPUTracerConfig(numLanes: Int, traceFile : String) // FIXME, add lane number and file name
case object GPUTracerKey extends Field[Option[GPUTracerConfig]](None)
// Both LazyModule of Tracer and Impl are both in Coalescing.scala
//The trait is attached to DigitalTop of Chipyard system, informing it indeed has the ability
//to attach GPU tracer node onto the system bus
// The trait is attached to DigitalTop of Chipyard system, informing it indeed
// has the ability to attach GPU tracer node onto the system bus
trait CanHaveGPUTracer { this: BaseSubsystem =>
implicit val p: Parameters
//p(GPUTracerKey) is the mechnimism to pass Config's parameter down to lazymodule
p(GPUTracerKey) .map { k =>
val config = p(GPUTracerKey).get
val tracer = LazyModule(new MemTraceDriver(defaultConfig, config.traceFile)(p))
// Must use :=* to ensure the N edges from Tracer doesn't get merged into 1 when connecting to SBus
p(SIMTCoreKey).map { _ =>
val config = p(SIMTCoreKey).get
val tracer = LazyModule(new MemTraceDriver(defaultConfig, config.tracefilename)(p))
// Must use :=* to ensure the N edges from Tracer doesn't get merged into 1
// when connecting to SBus
sbus.fromPort(Some("gpu-tracer"))() :=* tracer.node
}
}
//This is used by Chip Level Config, the config which creates the SoC
class WithGPUTracer(numLanes: Int, traceFile : String) extends Config((site, here, up) => {
case GPUTracerKey => Some( GPUTracerConfig(numLanes, traceFile) )
}
)
class WithGPUTracer(numLanes: Int, tracefilename: String)
extends Config((_, _, _) => { case SIMTCoreKey =>
Some(SIMTCoreParams(numLanes, tracefilename))
})