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Use WithoutTLMonitors to slightly speed up chiseltests

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This commit is contained in:
Hansung Kim
2023-05-08 14:38:15 -07:00
parent 54a3e3cf72
commit 2d4e28e862
1 changed files with 3 additions and 2 deletions
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5
src/test/scala/coalescing/CoalescingUnitTest.scala
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@@ -7,6 +7,7 @@ import org.scalatest.flatspec.AnyFlatSpec
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util.MultiPortQueue
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem.WithoutTLMonitors
import org.chipsalliance.cde.config.Parameters
import chisel3.util.{DecoupledIO, Valid}
import chisel3.util.experimental.BoringUtils
@@ -230,7 +231,7 @@ class CoalescerUnitTest extends AnyFlatSpec with ChiselScalatestTester {
}
it should "coalesce fully consecutive accesses at size 4, only once" in {
test(LazyModule(new DummyCoalescingUnitTB()).module)
test(LazyModule(new DummyCoalescingUnitTB()(new WithoutTLMonitors())).module)
.withAnnotations(Seq(VerilatorBackendAnnotation, VerilatorFlags(Seq("--coverage-line")), WriteFstAnnotation))
// .withAnnotations(Seq(VcsBackendAnnotation, WriteFsdbAnnotation))
{ c =>
@@ -292,7 +293,7 @@ class CoalescerUnitTest extends AnyFlatSpec with ChiselScalatestTester {
}
it should "coalesce identical addresses (stride of 0)" in {
test(LazyModule(new DummyCoalescingUnitTB()).module)
test(LazyModule(new DummyCoalescingUnitTB()(new WithoutTLMonitors())).module)
.withAnnotations(Seq(VerilatorBackendAnnotation))
{ c =>
println(s"coalIO length = ${c.coalIOs(0).length}")