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  • f07497638d Add .scalafmt.conf Hansung Kim 2023-03-27 14:38:02 -07:00
  • 434013f816 Remove redundant coal edge handling code Hansung Kim 2023-03-27 14:37:08 -07:00
  • d951de7810 Handle taking offset chunks in uncoalescing logic Hansung Kim 2023-03-27 14:22:21 -07:00
  • 4daa0cefd8 Check for response queue blocking Hansung Kim 2023-03-27 02:17:12 -07:00
  • d745792d42 Use rocket-chip MultiPortQueue to serialize responses Hansung Kim 2023-03-27 01:47:11 -07:00
  • 0660923eb8 Split out CoalescingUnitImp Hansung Kim 2023-03-27 01:12:28 -07:00
  • 2416275e12 Enqueue some uncoalesced data to response queue Hansung Kim 2023-03-27 00:58:03 -07:00
  • 683a0172d8 Fix sourceWidth being wrongly taken from coalescer edge Hansung Kim 2023-03-26 02:32:59 -07:00
  • a06911cf5b Make response queue, debug print for inflight entry Hansung Kim 2023-03-26 01:07:53 -07:00
  • 356aa9079f Make table RAM, not CAM Hansung Kim 2023-03-23 21:10:09 -07:00
  • 9f5b77145b Change inflight table entry to per-lane and per-srcId Hansung Kim 2023-03-19 02:08:17 -07:00
  • 08ce7dc57d Doc cleanup Hansung Kim 2023-03-19 01:17:11 -07:00
  • 2e06898dc0 Handle enqueue and lookup at the same cycle Hansung Kim 2023-03-13 16:22:22 -07:00
  • cb8ca183d5 Add debug counter for per-lane inflight reqs Hansung Kim 2023-03-13 15:37:52 -07:00
  • 400b356cfb Fix lookup succeeding on invalid entry; add test case Hansung Kim 2023-03-12 03:24:56 -07:00
  • 6de95587de Add chiseltest for inflight table Hansung Kim 2023-03-11 23:20:50 -08:00
  • df0c2ba89f Flip lookup signal flow Hansung Kim 2023-03-10 19:11:42 -08:00
  • 2ba03fc16d Write sourceId lookup logic for table Hansung Kim 2023-03-10 18:32:15 -08:00
  • 3887129994 Write enqueue and reset logic for table Hansung Kim 2023-03-10 18:00:38 -08:00
  • 9256b8f6a3 Write simple next-empty-entry finding logic Hansung Kim 2023-03-10 17:27:04 -08:00
  • 6866b537d6 Separate out InflightCoalReqTable into a module Hansung Kim 2023-03-10 15:28:28 -08:00
  • da58ab552f Construct entry for in-flight coalesced requests table Hansung Kim 2023-03-10 14:22:43 -08:00
  • 93b198e0f6 Properly assert ready/valid for all TL channels Hansung Kim 2023-03-10 00:21:06 -08:00
  • e523b4235a Make placeholder for inflight coalesced request table Hansung Kim 2023-03-09 23:48:12 -08:00
  • 13552593c8 Check legal from Get and Put Hansung Kim 2023-03-09 22:55:38 -08:00
  • 46d3109e82 Skip instantiating queue for the edge from master node Hansung Kim 2023-03-09 22:39:44 -08:00
  • 9bfb813e1b Thread -> Lane Hansung Kim 2023-03-09 22:09:07 -08:00
  • a495149869 Connect coal master node to identitynode internally Hansung Kim 2023-03-09 20:53:52 -08:00
  • f0069ba3ad Set lgSize=0 as memtrace addresses are not aligned Hansung Kim 2023-03-09 20:50:34 -08:00
  • babbdf9550 Left out fromSource Hansung Kim 2023-03-08 18:36:47 -08:00
  • 70b715645c Parameterize sourceId width for reg entry Hansung Kim 2023-03-08 18:32:06 -08:00
  • a2ceb8c628 Fix sourceId collision by using a counter Hansung Kim 2023-03-08 18:22:10 -08:00
  • f623cc89a7 Merged with origin/graphics, MemTracer able to read and write according to tracefile Vamber Yang 2023-03-08 17:38:59 -08:00
  • 0de09daa05 MemTracer able to read and write according to trace file, also support thread_id skipping in trace file Vamber Yang 2023-03-08 17:34:10 -08:00
  • 39db60f42b Queue -> ShiftQueue, preserve source id of incoming reqs Hansung Kim 2023-03-08 16:49:36 -08:00
  • 41ecf6bc20 Squelch debug prints in SimMemTrace Hansung Kim 2023-03-07 17:53:09 -08:00
  • 1bc8cbb925 Instantiate FIFOs to buffer TL reqs per each lane Hansung Kim 2023-03-07 15:10:00 -08:00
  • 337272764b Test with Get() and doc source ID allocation Hansung Kim 2023-03-06 23:15:30 -08:00
  • 760d3f5aa2 Add example where IdentityNode.out has different data from .in Hansung Kim 2023-03-06 21:56:56 -08:00
  • c7651e26f4 Organize Diplomacy node structure of CoalescingUnit Hansung Kim 2023-03-06 16:17:52 -08:00
  • aa2d52a197 Merge Coalescing{Logic, Entry} to CoalescingUnit Hansung Kim 2023-03-05 17:33:37 -08:00
  • 6fea4be050 Refactor with zip Hansung Kim 2023-03-05 16:59:06 -08:00
  • db9be56191 Properly connect each lane to TL node Hansung Kim 2023-03-05 00:18:29 -08:00
  • ef1608505f Use single SimMemTrace instance Hansung Kim 2023-03-04 21:57:47 -08:00
  • 172ab51355 Fix formatting and unused warnings Hansung Kim 2023-03-03 23:44:50 -08:00
  • 5f55a7578f Recover lost changes Hansung Kim 2023-03-03 22:36:54 -08:00
  • dcb49f7683 Doc update Hansung Kim 2023-03-03 21:16:42 -08:00
  • 1a322f5ca7 Merge remote-tracking branch 'origin/graphics' into HEAD Pulling remote changes before pushing Vamber Yang 2023-03-03 20:40:41 -08:00
  • c3129b8c5c Tracer supports N threads, communicates with Coalescing with TL + Diplomacy interface Vamber Yang 2023-03-03 20:27:29 -08:00
  • 97fec01620 Receive per-lane valid from SimMemTrace Hansung Kim 2023-03-03 18:09:58 -08:00
  • c1e8f4ef86 Maintain cycle inside Verilog instead of C Hansung Kim 2023-03-03 16:38:32 -08:00
  • 664959f723 Parameterize SimMemTrace Verilog module to number of threads Hansung Kim 2023-03-03 16:16:07 -08:00
  • 44cf6fbb2f Update SimMemTrace csrc from submodule Hansung Kim 2023-03-03 16:14:11 -08:00
  • b57c0e2b7d SimMemTrace: parse batch instead of at every cycle Hansung Kim 2023-03-02 17:24:36 -08:00
  • 24f4ee93ac Add TL client node to MemTraceDriver Hansung Kim 2023-02-27 23:35:14 -08:00
  • a06b5faa3c Wrap memtrace DPI module with a Chisel driver module Hansung Kim 2023-02-27 19:55:22 -08:00
  • 9025729c0e Emit address in addition to cycle Hansung Kim 2023-02-27 17:36:54 -08:00
  • 0ebaed5f1b Communicate trace cycle data from C++ to Chisel Hansung Kim 2023-02-27 14:40:49 -08:00
  • 72de4bca66 Initial parsing of memory trace file in C++ Hansung Kim 2023-02-27 13:46:19 -08:00
  • 80e4b5c734 Set up simple DPI for trace-driven testing Hansung Kim 2023-02-24 17:46:40 -08:00
  • 5bf8bb8217 Add empty unit test for coalescing unit Hansung Kim 2023-02-22 16:40:22 -08:00
  • 1b733e7cf0 Merge branch 'master' of github.com:ucb-bar/riscv-rocket Huy Vo 2012-03-13 12:34:39 -07:00
  • 2607153b67 Merge branch 'master' of github.com:ucb-bar/riscv-rocket Andrew Waterman 2012-03-09 02:08:55 -08:00
  • 4f00bcc760 Merge branch 'master' of github.com:ucb-bar/riscv-rocket Yunsup Lee 2012-02-29 17:12:02 -08:00
  • 0fd777f480 Merge branch 'master' of github.com:ucb-bar/riscv-rocket Huy Vo 2012-02-26 17:24:23 -08:00
  • 71c8d3fd41 reorganize directory structure Andrew Waterman 2012-02-08 15:13:08 -08:00