Connect smem core IO to TL with translation
This commit is contained in:
Hansung Kim
@@ -47,6 +47,8 @@ class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle
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val imemTagWidth = UUID_WIDTH + NW_WIDTH
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val LSUQ_TAG_BITS = 4
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val dmemTagWidth = UUID_WIDTH + LSUQ_TAG_BITS
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// dmem and smem shares the same tag width, DCACHE_NOSM_TAG_WIDTH
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val smemTagWidth = dmemTagWidth
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// conditionally instantiate ports depending on whether we want to use VX_cache or not
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val imem = if (!tile.vortexParams.useVxCache) Some(Vec(1, new Bundle {
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@@ -57,6 +59,10 @@ class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle
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val a = Decoupled(new VortexBundleA(tagWidth = dmemTagWidth, dataWidth = 32))
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val d = Flipped(Decoupled(new VortexBundleD(tagWidth = dmemTagWidth, dataWidth = 32)))
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})) else None
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val smem = if (!tile.vortexParams.useVxCache) Some(Vec(tile.numLanes, new Bundle {
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val a = Decoupled(new VortexBundleA(tagWidth = smemTagWidth, dataWidth = 32))
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val d = Flipped(Decoupled(new VortexBundleD(tagWidth = smemTagWidth, dataWidth = 32)))
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})) else None
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val mem = if (tile.vortexParams.useVxCache) Some(new Bundle {
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val a = Decoupled(new VortexBundleA(tagWidth = 15, dataWidth = 128))
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val d = Flipped(Decoupled(new VortexBundleD(tagWidth = 15, dataWidth = 128)))
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@@ -103,7 +109,6 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
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// addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v")
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// addResource("/vsrc/vortex/hw/syn/modelsim/vortex_tb.v")
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addResource("/vsrc/vortex/hw/rtl/VX_gpu_pkg.sv")
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// addResource("/vsrc/vortex/hw/rtl/VX_cluster.sv")
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@@ -341,6 +346,5 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
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}
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val nTotalRoCCCSRs = 0
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val coreBundle = new VortexBundle(tile)
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val io = IO(coreBundle)
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val io = IO(new VortexBundle(tile))
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}
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@@ -259,9 +259,8 @@ class VortexTile private (
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// NOTE: We need TLWidthWidget here because there might be a data width
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// mismatch between Vortex's per-lane response and the system bus when we
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// don't instantiate either L1 or the coalescer. This _should_ be optimized
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// out when we instantiate coalescer which should handle data width conversion
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// internally (which it does by... using TLWidthWidget), but probably not
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// the cleanest way to do this.
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// out when we instantiate either which should handle data width conversion
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// internally (which it does by... using TLWidthWidget).
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val dmemAggregateNode = TLIdentityNode()
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dmemNodes.foreach { dmemAggregateNode := TLWidthWidget(4) := _ }
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@@ -326,7 +325,8 @@ class VortexTile private (
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// Instantiate sharedmem
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// TODO: parametrize
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val sharedmem = LazyModule(new TLRAM(AddressSet(0xff000000L, 0x00ffffffL), beatBytes = 4 /*FIXME*/))
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// FIXME: beatBytes should be wordSize
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val sharedmem = LazyModule(new TLRAM(AddressSet(0xff000000L, 0x00ffffffL), beatBytes = 4))
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val smemXbar = LazyModule(new TLXbar)
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smemNodes.foreach(smemXbar.node := _)
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sharedmem.node :=* smemXbar.node
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@@ -492,95 +492,128 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
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outer.memNode.out(0)._1.a <> memTLAdapter.io.outReq
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memTLAdapter.io.outResp <> outer.memNode.out(0)._1.d
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} else {
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val imemTLAdapter = Module(
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new VortexTLAdapter(
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outer.imemSourceWidth,
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chiselTypeOf(core.io.imem.get(0).a.bits),
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chiselTypeOf(core.io.imem.get(0).d.bits),
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outer.imemNodes.head.out.head
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)
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)
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// TODO: make imemNodes not a vector
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imemTLAdapter.io.inReq <> core.io.imem.get(0).a
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core.io.imem.get(0).d <> imemTLAdapter.io.inResp
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outer.imemNodes(0).out(0)._1.a <> imemTLAdapter.io.outReq
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imemTLAdapter.io.outResp <> outer.imemNodes(0).out(0)._1.d
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// @perf: this would duplicate SourceGenerator table for every lane and eat
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// up some area
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val dmemTLBundles = outer.dmemNodes.map(_.out.head._1)
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val dmemTLAdapters = Seq.tabulate(outer.numLanes) { _ =>
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Module(
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def connectImem = {
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val imemTLAdapter = Module(
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new VortexTLAdapter(
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outer.dmemSourceWidth,
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chiselTypeOf(core.io.dmem.get(0).a.bits),
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chiselTypeOf(core.io.dmem.get(0).d.bits),
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outer.dmemNodes(0).out.head
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outer.imemSourceWidth,
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chiselTypeOf(core.io.imem.get(0).a.bits),
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chiselTypeOf(core.io.imem.get(0).d.bits),
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outer.imemNodes.head.out.head
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)
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)
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// TODO: make imemNodes not a vector
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imemTLAdapter.io.inReq <> core.io.imem.get(0).a
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core.io.imem.get(0).d <> imemTLAdapter.io.inResp
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outer.imemNodes(0).out(0)._1.a <> imemTLAdapter.io.outReq
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imemTLAdapter.io.outResp <> outer.imemNodes(0).out(0)._1.d
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}
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// Since the individual per-lane TL requests might come back out-of-sync between
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// the lanes, but Vortex core expects the per-lane responses to be synced,
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// we need to selectively fire responses that have the same source, and
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// delay others.
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//
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// In order to do that, we pick a source from one of the valid lanes using e.g.
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// an arbiter. Then using the chosen source id, we
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// - lie to core that response is not valid if source doesn't match picked, and
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// - lie to downstream that core is not ready if source doesn't match picked.
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//
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// Note that we cannot do this filtering logic using TileLink source ID, because
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// we're allocating source for each lane independently. In that case, it's
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// possible that lane 0's source matches lane 1/2/3's source by chance,
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// even when they originated from different warps. Using Vortex's dcache req tag
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// solves this issue because they use a UUID that is unique across all requests
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// in the program.
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//
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// TODO: A cleaner solution would be to simply do a synchronized allocation
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// of a same source id for all lanes.
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val arb = Module(
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new RRArbiter(
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core.io.dmem.get.head.d.bits.source.cloneType,
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outer.numLanes
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def connectDmem = {
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// @perf: this would duplicate SourceGenerator table for every lane and eat
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// up some area
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val dmemTLBundles = outer.dmemNodes.map(_.out.head._1)
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val dmemTLAdapters = Seq.tabulate(outer.numLanes) { _ =>
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Module(
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new VortexTLAdapter(
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outer.dmemSourceWidth,
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chiselTypeOf(core.io.dmem.get(0).a.bits),
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chiselTypeOf(core.io.dmem.get(0).d.bits),
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outer.dmemNodes(0).out.head
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)
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)
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}
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// Since the individual per-lane TL requests might come back out-of-sync between
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// the lanes, but Vortex core expects the per-lane responses to be synced,
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// we need to selectively fire responses that have the same source, and
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// delay others.
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//
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// In order to do that, we pick a source from one of the valid lanes using e.g.
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// an arbiter. Then using the chosen source id, we
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// - lie to core that response is not valid if source doesn't match picked, and
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// - lie to downstream that core is not ready if source doesn't match picked.
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//
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// Note that we cannot do this filtering logic using TileLink source ID, because
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// we're allocating source for each lane independently. In that case, it's
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// possible that lane 0's source matches lane 1/2/3's source by chance,
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// even when they originated from different warps. Using Vortex's dcache req tag
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// solves this issue because they use a UUID that is unique across all requests
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// in the program.
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//
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// TODO: A cleaner solution would be to simply do a synchronized allocation
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// of a same source id for all lanes.
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val arb = Module(
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new RRArbiter(
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core.io.dmem.get.head.d.bits.source.cloneType,
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outer.numLanes
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)
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)
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)
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arb.io.out.ready := true.B
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val dmemBundles = dmemTLAdapters.map(_.io.inResp)
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(arb.io.in zip dmemBundles).foreach { case (arbIn, vxDmem) =>
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arbIn.valid := vxDmem.valid
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arbIn.bits := vxDmem.bits.source
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}
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val matchingSources = Wire(UInt(outer.numLanes.W))
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matchingSources := dmemBundles
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.map(b =>
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// If there is no valid response pending across all lanes,
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// matchingSources should not filter out upstream ready signals, so
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// set it to all-1
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!arb.io.out.valid || (b.bits.source === arb.io.out.bits)
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)
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.asUInt
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arb.io.out.ready := true.B
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val dmemBundles = dmemTLAdapters.map(_.io.inResp)
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(arb.io.in zip dmemBundles).foreach { case (arbIn, vxDmem) =>
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arbIn.valid := vxDmem.valid
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arbIn.bits := vxDmem.bits.source
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}
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val matchingSources = Wire(UInt(outer.numLanes.W))
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matchingSources := dmemBundles
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.map(b =>
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// If there is no valid response pending across all lanes,
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// matchingSources should not filter out upstream ready signals, so
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// set it to all-1
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!arb.io.out.valid || (b.bits.source === arb.io.out.bits)
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)
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.asUInt
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// make connection:
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// VortexBundle <--> sourceId filter <--> VortexTLAdapter <--> dmemNodes
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(core.io.dmem.get zip dmemTLAdapters) foreach { case (coreMem, tlAdapter) =>
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tlAdapter.io.inReq <> coreMem.a
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coreMem.d <> tlAdapter.io.inResp
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}
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(core.io.dmem.get zip dmemTLAdapters).zipWithIndex.foreach {
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case ((coreMem, tlAdapter), i) =>
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coreMem.d.valid := tlAdapter.io.inResp.valid && matchingSources(i)
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tlAdapter.io.inResp.ready := coreMem.d.ready && matchingSources(i)
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}
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(dmemTLAdapters zip dmemTLBundles) foreach { case (tlAdapter, tlOut) =>
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tlOut.a <> tlAdapter.io.outReq
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tlAdapter.io.outResp <> tlOut.d
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// make connection:
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// VortexBundle <--> sourceId filter <--> VortexTLAdapter <--> dmemNodes
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(core.io.dmem.get zip dmemTLAdapters) foreach { case (coreMem, tlAdapter) =>
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tlAdapter.io.inReq <> coreMem.a
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coreMem.d <> tlAdapter.io.inResp
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}
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// override response channel with matchingSources
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(core.io.dmem.get zip dmemTLAdapters).zipWithIndex.foreach {
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case ((coreMem, tlAdapter), i) =>
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coreMem.d.valid := tlAdapter.io.inResp.valid && matchingSources(i)
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tlAdapter.io.inResp.ready := coreMem.d.ready && matchingSources(i)
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}
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(dmemTLAdapters zip dmemTLBundles) foreach { case (tlAdapter, tlOut) =>
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tlOut.a <> tlAdapter.io.outReq
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tlAdapter.io.outResp <> tlOut.d
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}
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outer.dmemAggregateNode.out.foreach { bo =>
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dontTouch(bo._1.a)
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dontTouch(bo._1.d)
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}
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}
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outer.dmemAggregateNode.out.foreach { bo =>
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dontTouch(bo._1.a)
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dontTouch(bo._1.d)
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def connectSmem = {
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// @perf: this would duplicate SourceGenerator table for every lane and eat
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// up some area
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val smemTLBundles = outer.smemNodes.map(_.out.head._1)
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val smemTLAdapters = Seq.tabulate(outer.numLanes) { _ =>
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Module(
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new VortexTLAdapter(
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outer.smemSourceWidth,
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chiselTypeOf(core.io.smem.get(0).a.bits),
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chiselTypeOf(core.io.smem.get(0).d.bits),
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outer.smemNodes(0).out.head
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)
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)
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}
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(core.io.smem.get zip smemTLAdapters) foreach { case (coreMem, tlAdapter) =>
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tlAdapter.io.inReq <> coreMem.a
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coreMem.d <> tlAdapter.io.inResp
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}
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(smemTLAdapters zip smemTLBundles) foreach { case (tlAdapter, tlOut) =>
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tlOut.a <> tlAdapter.io.outReq
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tlAdapter.io.outResp <> tlOut.d
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}
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}
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connectImem
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connectDmem
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connectSmem
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}
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// TODO: generalize for useVxCache
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