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Generate explicit clock domain in CanHaveMemtraceCore

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This commit is contained in:
Hansung Kim
2024-01-26 00:13:14 -08:00
parent 78075e5148
commit cfce029b70
1 changed files with 49 additions and 48 deletions
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97
src/main/scala/radiance/memory/CanHaveMemtraceCore.scala
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@@ -22,56 +22,57 @@ trait CanHaveMemtraceCore { this: BaseSubsystem =>
)
val numLanes = simtParam.nLanes
val filename = param.tracefilename
val tracer = LazyModule(
new MemTraceDriver(config, filename, param.traceHasSource)(p)
)
val coreSideLogger = LazyModule(
new MemTraceLogger(numLanes, filename, loggerName = "coreside")
)
val memSideLogger = LazyModule(
new MemTraceLogger(numLanes + 1, filename, loggerName = "memside")
)
// Must use :=* to ensure the N edges from Tracer doesn't get merged into 1
// when connecting to SBus
println(
s"============ MemTraceDriver instantiated [filename=${param.tracefilename}]"
)
val coalescerNode = p(CoalescerKey) match {
case Some(coalParam) => {
val coal = LazyModule(new CoalescingUnit(coalParam))
coal.cpuNode :=* coreSideLogger.node :=* tracer.node // N lanes
memSideLogger.node :=* coal.aggregateNode // N+1 lanes
memSideLogger.node
}
case None => tracer.node
}
val coalXbar = p(CoalXbarKey) match {
case Some(xbarParam) =>{
val coXbar = LazyModule(new TLXbar)
println(s"============ Using TLXBar for Coalescer Requests ")
coXbar.node :=* coalescerNode
coXbar.node
}
case None => coalescerNode
}
val vortexBank = coalXbar
//If there is only 1 bank, the code below is useless
val upstream = p(CoalXbarKey) match {
case Some(xbarParam) =>{
val tileXbar = LazyModule(new TLXbar)
println(s"============ Using TLXBar for L1 Requests ")
tileXbar.node :=* vortexBank
tileXbar.node
// Need to explicitly generate clock domain; see rocket-chip 8881ccd
val memtracerDomain = sbus.generateSynchronousDomain
memtracerDomain {
val tracer = LazyModule(
new MemTraceDriver(config, filename, param.traceHasSource)(p)
)
val coreSideLogger = LazyModule(
new MemTraceLogger(numLanes, filename, loggerName = "coreside")
)
val memSideLogger = LazyModule(
new MemTraceLogger(numLanes + 1, filename, loggerName = "memside")
)
// Must use :=* to ensure the N edges from Tracer doesn't get merged into 1
// when connecting to SBus
println(
s"============ MemTraceDriver instantiated [filename=${param.tracefilename}]"
)
val coalescerNode = p(CoalescerKey) match {
case Some(coalParam) => {
val coal = LazyModule(new CoalescingUnit(coalParam))
coal.cpuNode :=* coreSideLogger.node :=* tracer.node // N lanes
memSideLogger.node :=* coal.aggregateNode // N+1 lanes
memSideLogger.node
}
case None => tracer.node
}
val coalXbar = p(CoalXbarKey) match {
case Some(xbarParam) =>{
val coXbar = LazyModule(new TLXbar)
println(s"============ Using TLXBar for Coalescer Requests ")
coXbar.node :=* coalescerNode
coXbar.node
}
case None => coalescerNode
}
case None => vortexBank
}
sbus.coupleFrom(s"gpu-tracer") { _ :=* upstream }
val vortexBank = coalXbar
//If there is only 1 bank, the code below is useless
val upstream = p(CoalXbarKey) match {
case Some(xbarParam) =>{
val tileXbar = LazyModule(new TLXbar)
println(s"============ Using TLXBar for L1 Requests ")
tileXbar.node :=* vortexBank
tileXbar.node
}
case None => vortexBank
}
sbus.coupleFrom(s"gpu-tracer") { _ :=* upstream }
}
}
}