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Reduce sharedmem addr mapping to 8KB

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smem size is set to 16KB, and reqs exceeding this range gets filtered
out of smemNodes from inside the core.  Lower 8KB is mapped to smem
banks, and upper 8KB is reserved for MMIO.
This commit is contained in:
Hansung Kim
2024-01-23 22:14:15 -08:00
parent 17553ccfcd
commit df26764fc0
1 changed files with 1 additions and 1 deletions
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2
src/main/scala/radiance/tile/VortexTile.scala
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@@ -326,7 +326,7 @@ class VortexTile private (
// base for bank 1: ff...000000|01|00
// mask for bank 1; 00...111111|00|11
val base = 0xff000000L | (bankId * 4 /*wordSize*/ )
val mask = 0x00ffffffL ^ ((numLsuLanes - 1) * 4 /*wordSize*/ )
val mask = 0x00001fffL ^ ((numLsuLanes - 1) * 4 /*wordSize*/ )
LazyModule(new TLRAM(AddressSet(base, mask), beatBytes = 4 /*wordSize*/ ))
}
// smem lanes-to-banks crossbar