Add perf counters for smem/dmem latency
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@@ -617,6 +617,28 @@ class RadianceTileModuleImp(outer: RadianceTile)
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}
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core.io.dmem_d_valid := dmem_d_valid_vec.asUInt
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// performance counters
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val pendingReqsCumulative = RegInit(UInt(32.W), 0.U)
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val totalReqs = RegInit(UInt(32.W), 0.U)
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val reqFireCountPerCycle = PopCount(dmemTLAdapters.map(_.io.inReq.fire))
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val respFireCountPerCycle = PopCount(dmemTLAdapters.map(_.io.inResp.fire))
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totalReqs := totalReqs + reqFireCountPerCycle
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val pendingReqsPerCycle = reqFireCountPerCycle - respFireCountPerCycle
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pendingReqsCumulative := pendingReqsCumulative + pendingReqsPerCycle
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val prevFinished = RegNext(core.io.finished)
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val justFinished = !prevFinished && core.io.finished
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when (justFinished) {
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printf("PERF: dmem: pending requests cumulative: %d\n", pendingReqsCumulative)
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printf("PERF: dmem: total requests: %d\n", totalReqs)
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}
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dontTouch(totalReqs)
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dontTouch(pendingReqsCumulative)
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// now connect TL adapter downstream ports to the tile egress ports
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(dmemTLAdapters zip dmemTLBundles) foreach { case (tlAdapter, tlOut) =>
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tlOut.a <> tlAdapter.io.outReq
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tlAdapter.io.outResp <> tlOut.d
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@@ -666,6 +688,28 @@ class RadianceTileModuleImp(outer: RadianceTile)
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tlAdapter.io.inResp.ready := core.io.smem_d_ready(i)
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}
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// performance counters
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val pendingReqsCumulative = RegInit(UInt(32.W), 0.U)
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val totalReqs = RegInit(UInt(32.W), 0.U)
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val reqFireCountPerCycle = PopCount(smemTLAdapters.map(_.io.inReq.fire))
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val respFireCountPerCycle = PopCount(smemTLAdapters.map(_.io.inResp.fire))
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totalReqs := totalReqs + reqFireCountPerCycle
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val pendingReqsPerCycle = reqFireCountPerCycle - respFireCountPerCycle
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pendingReqsCumulative := pendingReqsCumulative + pendingReqsPerCycle
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val prevFinished = RegNext(core.io.finished)
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val justFinished = !prevFinished && core.io.finished
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when (justFinished) {
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printf("PERF: smem: pending requests cumulative: %d\n", pendingReqsCumulative)
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printf("PERF: smem: total requests: %d\n", totalReqs)
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}
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dontTouch(totalReqs)
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dontTouch(pendingReqsCumulative)
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// now connect TL adapter downstream ports to the tile egress ports
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(smemTLAdapters zip smemTLBundles) foreach { case (tlAdapter, tlOut) =>
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tlOut.a <> tlAdapter.io.outReq
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tlAdapter.io.outResp <> tlOut.d
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