restructure: initial filter pass
This commit is contained in:
Richard Yan
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../../../../hardfloat/berkeley-softfloat-3/source
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Submodule src/main/resources/vsrc/vortex updated: e7a3db6909...5ac0299f9c
225
src/main/scala/memory/UnitTest.scala
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225
src/main/scala/memory/UnitTest.scala
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.unittest
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import chisel3._
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import freechips.rocketchip.amba.ahb._
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import freechips.rocketchip.amba.apb._
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import freechips.rocketchip.amba.axi4._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.subsystem.{BaseSubsystemConfig}
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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import freechips.rocketchip.subsystem.WithSimtLanes
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//import rocket.VortexFatBankTest
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case object TestDurationMultiplier extends Field[Int]
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class WithTestDuration(x: Int) extends Config((site, here, up) => {
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case TestDurationMultiplier => x
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})
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class WithAMBAUnitTests extends Config((site, here, up) => {
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case UnitTests => (q: Parameters) => {
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implicit val p = q
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val txns = 100 * site(TestDurationMultiplier)
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val timeout = 50000 * site(TestDurationMultiplier)
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Seq(
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Module(new AHBBridgeTest(true, txns=8*txns, timeout=timeout)),
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Module(new AHBNativeTest(true, txns=6*txns, timeout=timeout)),
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Module(new AHBNativeTest(false, txns=6*txns, timeout=timeout)),
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Module(new APBBridgeTest(true, txns=6*txns, timeout=timeout)),
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Module(new APBBridgeTest(false, txns=6*txns, timeout=timeout)),
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Module(new AXI4LiteFuzzRAMTest( txns=6*txns, timeout=timeout)),
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Module(new AXI4LiteUserBitsFuzzRAMTest(txns=6*txns, timeout=timeout)),
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Module(new AXI4FullFuzzRAMTest( txns=3*txns, timeout=timeout)),
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Module(new AXI4BridgeTest( txns=3*txns, timeout=timeout)),
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Module(new AXI4XbarTest( txns=1*txns, timeout=timeout)),
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Module(new AXI4RAMAsyncCrossingTest( txns=3*txns, timeout=timeout)),
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Module(new AXI4RAMCreditedCrossingTest(txns=3*txns, timeout=timeout))) }
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})
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class WithTLSimpleUnitTests extends Config((site, here, up) => {
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case UnitTests => (q: Parameters) => {
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implicit val p = q
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val txns = 100 * site(TestDurationMultiplier)
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val timeout = 50000 * site(TestDurationMultiplier)
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Seq(
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Module(new TLRAMSimpleTest(1, true, txns=15*txns, timeout=timeout)),
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Module(new TLRAMSimpleTest(4, false,txns=15*txns, timeout=timeout)),
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Module(new TLRAMSimpleTest(16, true, txns=15*txns, timeout=timeout)),
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Module(new TLRAMZeroDelayTest(4, txns=15*txns, timeout=timeout)),
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Module(new TLRAMHintHandlerTest( txns=15*txns, timeout=timeout)),
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Module(new TLFuzzRAMTest( txns= 3*txns, timeout=timeout)),
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Module(new TLRR0Test( txns= 3*txns, timeout=timeout)),
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Module(new TLRR1Test( txns= 3*txns, timeout=timeout)),
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Module(new TLDecoupledArbiterLowestTest( txns= 3*txns, timeout=timeout)),
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Module(new TLDecoupledArbiterHighestTest(txns= 3*txns, timeout=timeout)),
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Module(new TLDecoupledArbiterRobinTest( txns= 3*txns, timeout=timeout)),
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Module(new TLRAMRationalCrossingTest(txns= 3*txns, timeout=timeout)),
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Module(new TLRAMAsyncCrossingTest( txns= 5*txns, timeout=timeout)),
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Module(new TLRAMCreditedCrossingTest(txns= 5*txns, timeout=timeout)),
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Module(new TLRAMAtomicAutomataTest( txns=10*txns, timeout=timeout)),
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Module(new TLRAMECCTest(8, 4, true, txns=15*txns, timeout=timeout)),
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Module(new TLRAMECCTest(4, 1, true, txns=15*txns, timeout=timeout)),
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Module(new TLRAMECCTest(1, 1, true, txns=15*txns, timeout=timeout)),
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Module(new TLRAMECCTest(8, 4, false, txns=15*txns, timeout=timeout)),
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Module(new TLRAMECCTest(4, 1, false, txns=15*txns, timeout=timeout)),
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Module(new TLRAMECCTest(1, 1, false, txns=15*txns, timeout=timeout)) ) }
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})
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class WithTLWidthUnitTests extends Config((site, here, up) => {
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case UnitTests => (q: Parameters) => {
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implicit val p = q
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val txns = 100 * site(TestDurationMultiplier)
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val timeout = 50000 * site(TestDurationMultiplier)
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Seq(
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Module(new TLRAMFragmenterTest( 4, 256, txns= 5*txns, timeout=timeout)),
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Module(new TLRAMFragmenterTest(16, 64, txns=15*txns, timeout=timeout)),
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Module(new TLRAMFragmenterTest( 4, 16, txns=15*txns, timeout=timeout)),
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Module(new TLRAMWidthWidgetTest( 1, 1, txns= 1*txns, timeout=timeout)),
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Module(new TLRAMWidthWidgetTest( 4, 64, txns= 4*txns, timeout=timeout)),
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Module(new TLRAMWidthWidgetTest(64, 4, txns= 5*txns, timeout=timeout)) ) }
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})
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class WithTLXbarUnitTests extends Config((site, here, up) => {
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case UnitTests => (q: Parameters) => {
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implicit val p = q
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val txns = 100 * site(TestDurationMultiplier)
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val timeout = 50000 * site(TestDurationMultiplier)
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Seq(
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Module(new TLJbarTest(3, 2, txns=5*txns, timeout=timeout)),
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Module(new TLRAMXbarTest(1, txns=5*txns, timeout=timeout)),
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Module(new TLRAMXbarTest(2, txns=5*txns, timeout=timeout)),
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Module(new TLRAMXbarTest(8, txns=5*txns, timeout=timeout)),
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Module(new TLMulticlientXbarTest(4,4, txns=2*txns, timeout=timeout)),
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Module(new TLMasterMuxTest( txns=5*txns, timeout=timeout)) ) }
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})
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class WithCoalescingUnitTests extends Config((site, _, _) => {
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case UnitTests => (q: Parameters) => {
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implicit val p = q
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val timeout = 50000 * site(TestDurationMultiplier)
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Seq(
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// Module(new TLRAMCoalescerTest(timeout=timeout)),
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Module(new TLRAMCoalescerLoggerTest(filename="vecadd.core1.thread4.trace", timeout=timeout)),
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// Module(new TLRAMCoalescerLoggerTest(filename="sfilter.core1.thread4.trace", timeout=timeout)),
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// Module(new TLRAMCoalescerLoggerTest(filename="nearn.core1.thread4.trace", timeout=50000000 * site(TestDurationMultiplier))),
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// Module(new TLRAMCoalescerLoggerTest(filename="psort.core1.thread4.trace", timeout=timeout)),
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// Module(new TLRAMCoalescerLoggerTest(filename="nvbit.vecadd.n100000.filter_sm0.trace", timeout=timeout)(new WithSimtLanes(32))),
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// Module(new TLRAMCoalescerLoggerTest(filename="nvbit.vecadd.n100000.filter_sm0.lane4.trace", timeout=timeout)),
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) }
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})
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/*
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class WithVortexFatBankUnitTests extends Config((site, _, _) => {
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case UnitTests => (q: Parameters) => {
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implicit val p = q
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val timeout = 50000 * site(TestDurationMultiplier)
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Seq(
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Module(new VortexFatBankTest(filename="oclprintf.core1.thread4.trace", timeout=timeout)),
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)}
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})
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*/
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class WithCoalescingUnitSynthesisDummy(nLanes: Int) extends Config((site, _, _) => {
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case UnitTests => (q: Parameters) => {
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implicit val p = q
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val timeout = 50000 * site(TestDurationMultiplier)
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Seq(
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Module(new DummyCoalescerTest(timeout=timeout)(new WithSimtLanes(nLanes=4))),
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) }
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})
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class WithECCTests extends Config((site, here, up) => {
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case UnitTests => (q: Parameters) => {
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Seq(
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// try some perfect codes
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Module(new ECCTest(1)), // n=3
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Module(new ECCTest(4)), // n=7
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Module(new ECCTest(11)), // n=15
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// try +1 perfect
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Module(new ECCTest(2)), // n=5
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Module(new ECCTest(5)), // n=9
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Module(new ECCTest(12)), // n=17
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// try -1 perfect
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Module(new ECCTest(3)), // n=6
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Module(new ECCTest(10)), // n=14
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// try a useful size
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Module(new ECCTest(8)) ) }
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})
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class WithScatterGatherTests extends Config((site, here, up) => {
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case UnitTests => (q: Parameters) => {
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Seq(
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Module(new GatherTest(1)),
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Module(new GatherTest(2)),
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Module(new GatherTest(3)),
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Module(new GatherTest(7)),
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Module(new GatherTest(8)),
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Module(new GatherTest(9)),
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Module(new ScatterTest(1)),
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Module(new ScatterTest(2)),
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Module(new ScatterTest(3)),
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Module(new ScatterTest(7)),
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Module(new ScatterTest(8)),
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Module(new ScatterTest(9)))}})
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class WithPLRUTests extends Config((site, here, up) => {
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case UnitTests => (q: Parameters) => {
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Seq(
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Module(new PLRUTest(2)),
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Module(new PLRUTest(3)),
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Module(new PLRUTest(4)),
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Module(new PLRUTest(5)),
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Module(new PLRUTest(6)))}})
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class WithPowerQueueTests extends Config((site, here, up) => {
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case UnitTests => (q: Parameters) => {
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Seq(
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Module(new PositionedQueueTest(FloppedLanePositionedQueue, 1, 2, false, false, 10000)),
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Module(new PositionedQueueTest(FloppedLanePositionedQueue, 2, 6, false, false, 10000)),
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Module(new PositionedQueueTest(FloppedLanePositionedQueue, 3, 10, false, false, 10000)),
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Module(new PositionedQueueTest(FloppedLanePositionedQueue, 2, 8, false, true, 10000)),
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Module(new PositionedQueueTest(FloppedLanePositionedQueue, 4, 8, true, false, 10000)),
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Module(new PositionedQueueTest(FloppedLanePositionedQueue, 1, 16, true, true, 10000)),
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Module(new PositionedQueueTest(FloppedLanePositionedQueue, 4, 2, true, true, 10000)),
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Module(new PositionedQueueTest(OnePortLanePositionedQueue(new IdentityCode), 4, 12, false, false, 10000)),
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Module(new PositionedQueueTest(OnePortLanePositionedQueue(new IdentityCode), 4, 16, false, false, 10000)),
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Module(new PositionedQueueTest(OnePortLanePositionedQueue(new IdentityCode), 4, 20, false, false, 10000)),
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Module(new PositionedQueueTest(OnePortLanePositionedQueue(new IdentityCode), 1, 12, false, false, 10000)),
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Module(new PositionedQueueTest(OnePortLanePositionedQueue(new IdentityCode), 3, 16, false, false, 10000)),
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Module(new PositionedQueueTest(OnePortLanePositionedQueue(new IdentityCode), 5, 20, false, false, 10000)),
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Module(new PositionedQueueTest(OnePortLanePositionedQueue(new IdentityCode), 2, 32, true, false, 10000)),
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Module(new PositionedQueueTest(OnePortLanePositionedQueue(new IdentityCode), 2, 16, false, true, 10000)),
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Module(new PositionedQueueTest(OnePortLanePositionedQueue(new IdentityCode), 4, 8, true, true, 10000)),
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Module(new PositionedQueueTest(OnePortLanePositionedQueue(new IdentityCode), 1, 16, true, true, 10000)),
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Module(new PositionedQueueTest(OnePortLanePositionedQueue(new IdentityCode), 2, 8, true, true, 10000)),
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Module(new MultiPortQueueTest(1, 1, 2, 10000)),
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Module(new MultiPortQueueTest(3, 3, 2, 10000)),
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Module(new MultiPortQueueTest(5, 5, 6, 10000)),
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Module(new MultiPortQueueTest(4, 3, 6, 10000)),
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Module(new MultiPortQueueTest(4, 5, 2, 10000)),
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Module(new MultiLaneQueueTest(1, 2, 10000)),
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Module(new MultiLaneQueueTest(3, 2, 10000)),
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Module(new MultiLaneQueueTest(5, 6, 10000))
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)}})
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class AMBAUnitTestConfig extends Config(new WithAMBAUnitTests ++ new WithTestDuration(10) ++ new BaseSubsystemConfig)
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class TLSimpleUnitTestConfig extends Config(new WithTLSimpleUnitTests ++ new WithTestDuration(10) ++ new BaseSubsystemConfig)
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class TLWidthUnitTestConfig extends Config(new WithTLWidthUnitTests ++ new WithTestDuration(10) ++ new BaseSubsystemConfig)
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class TLXbarUnitTestConfig extends Config(new WithTLXbarUnitTests ++ new WithTestDuration(10) ++ new BaseSubsystemConfig)
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class CoalescingUnitTestConfig extends Config(new WithCoalescingUnitTests ++ new WithTestDuration(10) ++ new WithSimtLanes(nLanes=4) ++ new BaseSubsystemConfig)
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//class VortexFatBankUnitTestConfig extends Config(new WithVortexFatBankUnitTests ++ new WithTestDuration(10) ++ new WithSimtLanes(nLanes=4) ++ new BaseSubsystemConfig)
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class ECCUnitTestConfig extends Config(new WithECCTests)
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class ScatterGatherTestConfig extends Config(new WithScatterGatherTests)
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class PLRUUnitTestConfig extends Config(new WithPLRUTests)
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class PowerQueueTestConfig extends Config(new WithPowerQueueTests)
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// Dummy configs of various sizes for synthesis
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class CoalescingSynthesisDummyLane4Config extends Config(new WithCoalescingUnitSynthesisDummy(4) ++ new WithTestDuration(10) ++ new BaseSubsystemConfig)
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class CoalescingSynthesisDummyLane8Config extends Config(new WithCoalescingUnitSynthesisDummy(8) ++ new WithTestDuration(10) ++ new BaseSubsystemConfig)
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class CoalescingSynthesisDummyLane16Config extends Config(new WithCoalescingUnitSynthesisDummy(16) ++ new WithTestDuration(10) ++ new BaseSubsystemConfig)
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class CoalescingSynthesisDummyLane32Config extends Config(new WithCoalescingUnitSynthesisDummy(32) ++ new WithTestDuration(10) ++ new BaseSubsystemConfig)
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