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Flatten smem bundle of Vortex core IO into 1-D arrays

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This commit is contained in:
Hansung Kim
2024-01-04 00:53:18 -08:00
parent 60cd72a9d6
commit 51e17e709b
2 changed files with 44 additions and 8 deletions
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20
src/main/scala/rocket/VortexCore.scala
View File

@@ -50,8 +50,8 @@ class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle
// val d = Flipped(Decoupled(new VortexBundleD(tagWidth = dmemTagWidth, dataWidth = 32)))
})) else None
val smem = if (!tile.vortexParams.useVxCache) Some(Vec(tile.numLanes, new Bundle {
val a = Decoupled(new VortexBundleA(tagWidth = tile.smemTagWidth, dataWidth = 32))
val d = Flipped(Decoupled(new VortexBundleD(tagWidth = tile.smemTagWidth, dataWidth = 32)))
// val a = Decoupled(new VortexBundleA(tagWidth = tile.smemTagWidth, dataWidth = 32))
// val d = Flipped(Decoupled(new VortexBundleD(tagWidth = tile.smemTagWidth, dataWidth = 32)))
})) else None
val mem = if (tile.vortexParams.useVxCache) Some(new Bundle {
val a = Decoupled(new VortexBundleA(tagWidth = 15, dataWidth = 128))
@@ -80,6 +80,22 @@ class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle
val dmem_d_bits_data = Input(UInt((tile.numLanes * 32).W))
val dmem_d_ready = Output(UInt((tile.numLanes * 1).W))
val smem_a_ready = Input(UInt((tile.numLanes * 1).W))
val smem_a_valid = Output(UInt((tile.numLanes * 1).W))
val smem_a_bits_opcode = Output(UInt((tile.numLanes * 3).W))
val smem_a_bits_size = Output(UInt((tile.numLanes * 4).W))
val smem_a_bits_source = Output(UInt((tile.numLanes * tile.smemTagWidth).W))
val smem_a_bits_address = Output(UInt((tile.numLanes * 32).W))
val smem_a_bits_mask = Output(UInt((tile.numLanes * 4).W))
val smem_a_bits_data = Output(UInt((tile.numLanes * 32).W))
val smem_d_valid = Input(UInt((tile.numLanes * 1).W))
val smem_d_bits_opcode = Input(UInt((tile.numLanes * 3).W))
val smem_d_bits_size = Input(UInt((tile.numLanes * 4).W))
val smem_d_bits_source = Input(UInt((tile.numLanes * tile.smemTagWidth).W))
val smem_d_bits_data = Input(UInt((tile.numLanes * 32).W))
val smem_d_ready = Output(UInt((tile.numLanes * 1).W))
// val fpu = Flipped(new FPUCoreIO())
//val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs))
//val trace = Output(new TraceBundle)

32
src/main/scala/tile/VortexTile.scala
View File

@@ -616,6 +616,7 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
tlAdapter.io.inResp.ready := core.io.dmem_d_ready(i) && matchingSources(i)
}
core.io.dmem_d_valid := dmem_d_valid_vec.asUInt
(dmemTLAdapters zip dmemTLBundles) foreach { case (tlAdapter, tlOut) =>
tlOut.a <> tlAdapter.io.outReq
tlAdapter.io.outResp <> tlOut.d
@@ -635,17 +636,36 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
Module(
new VortexTLAdapter(
outer.smemSourceWidth,
chiselTypeOf(core.io.smem.get(0).a.bits),
chiselTypeOf(core.io.smem.get(0).d.bits),
new VortexBundleA(tagWidth = outer.smemTagWidth, dataWidth = 32),
new VortexBundleD(tagWidth = outer.smemTagWidth, dataWidth = 32),
outer.smemNodes(0).out.head
)
)
}
(core.io.smem.get zip smemTLAdapters) foreach {
case (coreMem, tlAdapter) =>
tlAdapter.io.inReq <> coreMem.a
coreMem.d <> tlAdapter.io.inResp
smemTLAdapters.zipWithIndex.foreach {
case (tlAdapter, i) =>
// tlAdapter.io.inReq <> coreMem.a
tlAdapter.io.inReq.valid := core.io.smem_a_valid(i)
tlAdapter.io.inReq.bits.opcode := core.io.smem_a_bits_opcode(3 * (i + 1) - 1, 3 * i)
tlAdapter.io.inReq.bits.size := core.io.smem_a_bits_size(4 * (i + 1) - 1, 4 * i)
tlAdapter.io.inReq.bits.source := core.io.smem_a_bits_source(outer.smemTagWidth * (i + 1) - 1, outer.smemTagWidth * i)
tlAdapter.io.inReq.bits.address := core.io.smem_a_bits_address(32 * (i + 1) - 1, 32 * i)
tlAdapter.io.inReq.bits.mask := core.io.smem_a_bits_mask(4 * (i + 1) - 1, 4 * i)
tlAdapter.io.inReq.bits.data := core.io.smem_a_bits_data(32 * (i + 1) - 1, 32 * i)
}
core.io.smem_a_ready := smemTLAdapters.map(_.io.inReq.ready).asUInt
core.io.smem_d_valid := smemTLAdapters.map(_.io.inResp.valid).asUInt
core.io.smem_d_bits_opcode := smemTLAdapters.map(_.io.inResp.bits.opcode).asUInt
core.io.smem_d_bits_size := smemTLAdapters.map(_.io.inResp.bits.size).asUInt
core.io.smem_d_bits_source := smemTLAdapters.map(_.io.inResp.bits.source).asUInt
core.io.smem_d_bits_data := smemTLAdapters.map(_.io.inResp.bits.data).asUInt
smemTLAdapters.zipWithIndex.foreach {
case (tlAdapter, i) =>
tlAdapter.io.inResp.ready := core.io.smem_d_ready(i)
}
(smemTLAdapters zip smemTLBundles) foreach { case (tlAdapter, tlOut) =>
tlOut.a <> tlAdapter.io.outReq
tlAdapter.io.outResp <> tlOut.d