Merge branch 'main' of https://github.com/ucb-bar/radiance into main

src/main/scala/radiance/tile/RadianceTile.scala

@@ -356,19 +356,17 @@ class VortexTile private (
   tlMasterXbar.node :=* AddressRewriterNode(base) :=* gemmini.atlNode
   tlOtherMastersNode :=* AddressRewriterNode(base) :=* gemmini.tlNode
 
+  // MMIO
   gemmini.stlNode :=* TLWidthWidget(4) :=* smemXbar.node
+  // sharedmem access
+  //
+  // FIXME: gemmini spad has 16B data width; core smem interface has 4B. Need
+  // to consolidate by either coalescing, or changing gemmini spad to
+  // strided-by-word
   gemmini.unified_mem_node :=* TLWidthWidget(4) :=* smemXbar.node
 
   /* below are copied from rocket */
 
-  // val bus_error_unit = vortexParams.beuAddr map { a =>
-  //   val beu =
-  //     LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a)))
-  //   intOutwardNode := beu.intNode
-  //   connectTLSlave(beu.node, xBytes)
-  //   beu
-  // }
-
   val tile_master_blocker =
     tileParams.blockerCtrlAddr
       .map(
@@ -469,10 +467,6 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
 
   outer.decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector
 
-  // outer.bus_error_unit.foreach { beu =>
-  //   core.io.interrupts.buserror.get := beu.module.io.interrupt
-  // }
-
   core.io.interrupts.nmi.foreach { nmi => nmi := outer.nmiSinkNode.get.bundle }
 
   // Pass through various external constants and reports that were bundle-bridged into the tile