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Fix undefined {MEM,WORD}_ADDR_SIZE

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This commit is contained in:
Hansung Kim
2023-11-28 22:49:48 -08:00
parent 0589b310f1
commit 2bdaf3a0a8
1 changed files with 7 additions and 2 deletions
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9
src/main/scala/rocket/VortexBank.scala
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@@ -444,6 +444,11 @@ class VX_cache_top(
log2Ceil(mshrSize) + log2Ceil(numBanks)
val MEM_TAG_WIDTH = memTagWidth(MSHR_SIZE, 1/* NUM_BANKS */)
// These logic is fixed in VX_cache_define.vh
val memAddrWidth = 32 // FIXME hardcoded
val cacheWordAddrWidth = 32 - log2Ceil(WORD_SIZE)
val cacheMemAddrWidth = 32 - log2Ceil(CACHE_LINE_SIZE)
val io = IO(new Bundle {
val clk = Input(Clock())
val reset = Input(Reset())
@@ -452,7 +457,7 @@ class VX_cache_top(
val core_req_valid = Input(Bool())
val core_req_rw = Input(Bool())
val core_req_byteen = Input(UInt(WORD_SIZE.W))
val core_req_addr = Input(UInt(WORD_ADDR_WIDTH.W))
val core_req_addr = Input(UInt(cacheWordAddrWidth.W))
val core_req_data = Input(UInt((WORD_SIZE * 8).W))
val core_req_tag = Input(UInt(CORE_TAG_WIDTH.W))
val core_req_ready = Output(Bool())
@@ -466,7 +471,7 @@ class VX_cache_top(
val mem_req_valid = Output(Bool())
val mem_req_rw = Output(Bool())
val mem_req_byteen = Output(UInt(CACHE_LINE_SIZE.W))
val mem_req_addr = Output(UInt(MEM_ADDR_WIDTH.W))
val mem_req_addr = Output(UInt(cacheMemAddrWidth.W))
val mem_req_data = Output(UInt((CACHE_LINE_SIZE * 8).W))
val mem_req_tag = Output(UInt(MEM_TAG_WIDTH.W))
val mem_req_ready = Input(Bool())