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Comment out hartid and fpu from VortexBundle

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These are mostly copied from Rocket and we're not sure they're necessary
for Vortex.
This commit is contained in:
Hansung Kim
2023-10-11 20:29:15 -07:00
parent acc66e413a
commit dab1d907d6
2 changed files with 9 additions and 6 deletions
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4
src/main/scala/rocket/VortexCore.scala
View File

@@ -15,7 +15,7 @@ import tile.VortexTile
class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle {
val clock = Input(Clock())
val reset = Input(Reset())
val hartid = Input(UInt(hartIdLen.W))
// val hartid = Input(UInt(hartIdLen.W))
val reset_vector = Input(UInt(resetVectorLen.W))
val interrupts = Input(new CoreInterrupts())
@@ -33,7 +33,7 @@ class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle
val d = Flipped(tile.memNode.out.head._1.d.cloneType)
}) else None
val fpu = Flipped(new FPUCoreIO())
// val fpu = Flipped(new FPUCoreIO())
//val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs))
//val trace = Output(new TraceBundle)
//val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth)))

11
src/main/scala/tile/VortexTile.scala
View File

@@ -203,9 +203,11 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
// outer.traceSourceNode.bundle <> core.io.trace
core.io.traceStall := outer.traceAuxSinkNode.bundle.stall
// outer.bpwatchSourceNode.bundle <> core.io.bpwatch
core.io.hartid := outer.hartIdSinkNode.bundle
require(core.io.hartid.getWidth >= outer.hartIdSinkNode.bundle.getWidth,
s"core hartid wire (${core.io.hartid.getWidth}b) truncates external hartid wire (${outer.hartIdSinkNode.bundle.getWidth}b)")
// Copypasted from Rocket; not necessary for Vortex as hartId is set via Verilog parameter
// core.io.hartid := outer.hartIdSinkNode.bundle
// require(core.io.hartid.getWidth >= outer.hartIdSinkNode.bundle.getWidth,
// s"core hartid wire (${core.io.hartid.getWidth}b) truncates external hartid wire (${outer.hartIdSinkNode.bundle.getWidth}b)")
if (outer.vortexParams.useVxCache) {
println(s"width of a channel data ${core.io.mem.get.a.bits.data.getWidth}")
@@ -245,7 +247,7 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
}
}
core.io.fpu := DontCare
// core.io.fpu := DontCare
// TODO eliminate this redundancy
// val h = dcachePorts.size
@@ -257,6 +259,7 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
// dcacheArb.io.requestor <> dcachePorts.toSeq
}
// FIXME: unsure this is necessary
trait HasFpuOpt { this: RocketTileModuleImp =>
val fpuOpt = outer.tileParams.core.fpu.map(params => Module(new FPU(params)(outer.p)))
}