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add vortex cache temporarily

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This commit is contained in:
joshua
2023-09-23 13:03:53 -07:00
parent 7c5281cd0e
commit e3f85da12c
2 changed files with 108 additions and 80 deletions
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94
src/main/scala/rocket/VortexCore.scala
View File

@@ -12,6 +12,36 @@ import freechips.rocketchip.util._
import freechips.rocketchip.scie._
import tile.VortexTile
class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle {
val clock = Input(Clock())
val reset = Input(Reset())
val hartid = Input(UInt(hartIdLen.W))
val reset_vector = Input(UInt(resetVectorLen.W))
val interrupts = Input(new CoreInterrupts())
// conditionally instantiate ports depending on whether we want to use VX_cache or not
val imem = if (!tile.vortexParams.useVxCache) Some(Vec(1, new Bundle { // TODO: magic number
val a = tile.imemNodes.head.out.head._1.a.cloneType
val d = Flipped(tile.imemNodes.head.out.head._1.d.cloneType)
})) else None
val dmem = if (!tile.vortexParams.useVxCache) Some(Vec(4, new Bundle {
val a = tile.dmemNodes.head.out.head._1.a.cloneType
val d = Flipped(tile.dmemNodes.head.out.head._1.d.cloneType)
})) else None
val mem = if (tile.vortexParams.useVxCache) Some(new Bundle {
val a = tile.memNode.out.head._1.a.cloneType
val d = Flipped(tile.memNode.out.head._1.d.cloneType)
}) else None
val fpu = Flipped(new FPUCoreIO())
//val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs))
//val trace = Output(new TraceBundle)
//val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth)))
val cease = Output(Bool())
val wfi = Output(Bool())
val traceStall = Input(Bool())
}
class Vortex(tile: VortexTile)(implicit p: Parameters)
extends BlackBox with HasBlackBoxResource {
// addResource("/vsrc/vortex/hw/unit_tests/generic_queue/testbench.v")
@@ -33,17 +63,9 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
// addResource("/vsrc/vortex/hw/syn/modelsim/vortex_tb.v")
addResource("/vsrc/vortex/hw/rtl/VX_dispatch.sv")
addResource("/vsrc/vortex/hw/rtl/VX_issue.sv")
// addResource("/vsrc/vortex/hw/rtl/cache/VX_shared_mem.sv")
// addResource("/vsrc/vortex/hw/rtl/cache/VX_core_rsp_merge.sv")
// addResource("/vsrc/vortex/hw/rtl/cache/VX_tag_access.sv")
// addResource("/vsrc/vortex/hw/rtl/cache/VX_core_req_bank_sel.sv")
// addResource("/vsrc/vortex/hw/rtl/cache/VX_bank.sv")
// addResource("/vsrc/vortex/hw/rtl/cache/VX_cache.sv")
// addResource("/vsrc/vortex/hw/rtl/cache/VX_data_access.sv")
addResource("/vsrc/vortex/hw/rtl/cache/VX_cache_define.vh")
// addResource("/vsrc/vortex/hw/rtl/cache/VX_flush_ctrl.sv")
// addResource("/vsrc/vortex/hw/rtl/cache/VX_nc_bypass.sv")
// addResource("/vsrc/vortex/hw/rtl/cache/VX_miss_resrv.sv")
addResource("/vsrc/vortex/hw/rtl/VX_warp_sched.sv")
// addResource("/vsrc/vortex/hw/rtl/Vortex.sv")
addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_sat.sv")
@@ -72,7 +94,6 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
// unused addResource("/vsrc/vortex/hw/rtl/libs/VX_mux.sv")
addResource("/vsrc/vortex/hw/rtl/libs/VX_lzc.sv")
addResource("/vsrc/vortex/hw/rtl/libs/VX_fifo_queue.sv")
// unused addResource("/vsrc/vortex/hw/rtl/libs/VX_scope.sv")
addResource("/vsrc/vortex/hw/rtl/libs/VX_scan.sv")
addResource("/vsrc/vortex/hw/rtl/libs/VX_find_first.sv")
addResource("/vsrc/vortex/hw/rtl/libs/VX_multiplier.sv")
@@ -98,7 +119,7 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
// unused addResource("/vsrc/vortex/hw/rtl/libs/VX_bypass_buffer.sv")
addResource("/vsrc/vortex/hw/rtl/libs/VX_sp_ram.sv")
addResource("/vsrc/vortex/hw/rtl/libs/VX_stream_demux.sv")
// addResource("/vsrc/vortex/hw/rtl/libs/VX_pending_size.sv")
addResource("/vsrc/vortex/hw/rtl/libs/VX_pending_size.sv")
// unused addResource("/vsrc/vortex/hw/rtl/libs/VX_index_queue.sv")
addResource("/vsrc/vortex/hw/rtl/libs/VX_serial_div.sv")
addResource("/vsrc/vortex/hw/rtl/libs/VX_fair_arbiter.sv")
@@ -110,13 +131,11 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
addResource("/vsrc/vortex/hw/rtl/VX_execute.sv")
addResource("/vsrc/vortex/hw/rtl/VX_fetch.sv")
addResource("/vsrc/vortex/hw/rtl/VX_alu_unit.sv")
// unused addResource("/vsrc/vortex/hw/rtl/VX_mem_arb.sv")
addResource("/vsrc/vortex/hw/rtl/VX_platform.vh")
addResource("/vsrc/vortex/hw/rtl/VX_commit.sv")
// unused addResource("/vsrc/vortex/hw/rtl/VX_smem_arb.sv")
addResource("/vsrc/vortex/hw/rtl/VX_pipeline.sv")
addResource("/vsrc/vortex/hw/rtl/VX_lsu_unit.sv")
// addResource("/vsrc/vortex/hw/rtl/VX_mem_unit.sv")
addResource("/vsrc/vortex/hw/rtl/VX_csr_unit.sv")
// addResource("/vsrc/vortex/hw/rtl/Vortex_axi.sv")
// addResource("/vsrc/vortex/hw/rtl/fp_cores/VX_fp_div.sv")
@@ -196,30 +215,27 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
// addResource("/vsrc/vortex/hw/rtl/afu/VX_avs_wrapper.sv")
// addResource("/vsrc/vortex/hw/rtl/afu/VX_to_mem.sv")
// addResource("/vsrc/vortex/sim/vlsim/vortex_afu_shim.sv")
addResource("/vsrc/vortex/hw/rtl/VX_pipeline_wrapper.sv")
if (tile.vortexParams.useVxCache) {
addResource("/vsrc/vortex/hw/rtl/cache/VX_shared_mem.sv")
addResource("/vsrc/vortex/hw/rtl/cache/VX_core_rsp_merge.sv")
addResource("/vsrc/vortex/hw/rtl/cache/VX_tag_access.sv")
addResource("/vsrc/vortex/hw/rtl/cache/VX_core_req_bank_sel.sv")
addResource("/vsrc/vortex/hw/rtl/cache/VX_bank.sv")
addResource("/vsrc/vortex/hw/rtl/cache/VX_data_access.sv")
addResource("/vsrc/vortex/hw/rtl/cache/VX_flush_ctrl.sv")
addResource("/vsrc/vortex/hw/rtl/cache/VX_nc_bypass.sv")
addResource("/vsrc/vortex/hw/rtl/cache/VX_miss_resrv.sv")
addResource("/vsrc/vortex/hw/rtl/cache/VX_cache.sv")
addResource("/vsrc/vortex/hw/rtl/VX_mem_arb.sv")
addResource("/vsrc/vortex/hw/rtl/VX_smem_arb.sv")
addResource("/vsrc/vortex/hw/rtl/VX_mem_unit.sv")
addResource("/vsrc/vortex/hw/rtl/VX_core.sv")
addResource("/vsrc/vortex/hw/rtl/VX_core_wrapper.sv")
} else {
addResource("/vsrc/vortex/hw/rtl/VX_pipeline_wrapper.sv")
}
val nTotalRoCCCSRs = 0
val io = IO(new CoreBundle()(p) {
val clock = Input(Clock())
val reset = Input(Reset())
val hartid = Input(UInt(hartIdLen.W))
val reset_vector = Input(UInt(resetVectorLen.W))
val interrupts = Input(new CoreInterrupts())
val imem = Vec(1, new Bundle { // TODO: magic number
val a = tile.imemNodes.head.out.head._1.a.cloneType
val d = Flipped(tile.imemNodes.head.out.head._1.d.cloneType)
})
val dmem = Vec(4, new Bundle {
val a = tile.dmemNodes.head.out.head._1.a.cloneType
val d = Flipped(tile.dmemNodes.head.out.head._1.d.cloneType)
})
val fpu = Flipped(new FPUCoreIO())
//val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs))
//val trace = Output(new TraceBundle)
//val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth)))
val cease = Output(Bool())
val wfi = Output(Bool())
val traceStall = Input(Bool())
})
val coreBundle = new VortexBundle(tile)
val io = IO(coreBundle)
}

94
src/main/scala/tile/VortexTile.scala
View File

@@ -23,22 +23,8 @@ case class RocketTileBoundaryBufferParams(force: Boolean = false)
case class VortexTileParams(
core: RocketCoreParams = RocketCoreParams(),
icache: Option[ICacheParams] = Some(ICacheParams(
nSets = 64,
nWays = 4,
rowBits = 128,
nTLBSets = 1,
nTLBWays = 32,
nTLBBasePageSectors = 4,
nTLBSuperpages = 4,
cacheIdBits = 0,
blockBytes = 64,
latency = 2,
fetchBytes = 4
)),
dcache: Option[DCacheParams] = Some(DCacheParams(
// TODO
)),
icache: Option[ICacheParams] = None /* Some(ICacheParams()) */,
dcache: Option[DCacheParams] = None /* Some(DCacheParams()) */,
btb: Option[BTBParams] = None, // Some(BTBParams()),
dataScratchpadBytes: Int = 0,
name: Option[String] = Some("vortex_tile"),
@@ -48,8 +34,12 @@ case class VortexTileParams(
clockSinkParams: ClockSinkParameters = ClockSinkParameters(),
boundaryBuffers: Option[RocketTileBoundaryBufferParams] = None
) extends InstantiableTileParams[VortexTile] {
require(icache.isDefined)
require(dcache.isDefined)
// require(icache.isDefined)
// require(dcache.isDefined)
require(icache.isDefined == dcache.isDefined)
def useVxCache: Boolean = !icache.isDefined;
def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): VortexTile = {
new VortexTile(this, crossing, lookup)
}
@@ -111,8 +101,24 @@ class VortexTile private(
))
)))}
imemNodes.foreach { tlMasterXbar.node := _ }
dmemNodes.foreach { tlMasterXbar.node := _ }
val memNode = TLClientNode(Seq(TLMasterPortParameters.v1(
clients = Seq(TLMasterParameters.v1(
sourceId = IdRange(0, 1 << 10), // TODO magic number
name = s"Vortex Core ${vortexParams.hartId} Mem Interface",
requestFifo = true,
supportsProbe = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
supportsGet = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
supportsPutFull = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
supportsPutPartial = TransferSizes(1, lazyCoreParamsView.coreDataBytes)
))
)))
if (vortexParams.useVxCache) {
tlMasterXbar.node := memNode
} else {
imemNodes.foreach { tlMasterXbar.node := _ }
dmemNodes.foreach { tlMasterXbar.node := _ }
}
val bus_error_unit = vortexParams.beuAddr map { a =>
val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a)))
@@ -172,7 +178,7 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
Annotated.params(this, outer.vortexParams)
val core = Module(new Vortex(outer)(outer.p))
core.io.clock := clock
core.io.reset := reset
@@ -201,31 +207,37 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
require(core.io.hartid.getWidth >= outer.hartIdSinkNode.bundle.getWidth,
s"core hartid wire (${core.io.hartid.getWidth}b) truncates external hartid wire (${outer.hartIdSinkNode.bundle.getWidth}b)")
(core.io.imem zip outer.imemNodes).foreach { case (coreMem, tileNode) =>
coreMem.d <> tileNode.out.head._1.d
coreMem.a <> tileNode.out.head._1.a
if (outer.vortexParams.useVxCache) {
core.io.mem.get.a <> outer.memNode.out.head._1.a
core.io.mem.get.d <> outer.memNode.out.head._1.d
}
else {
(core.io.imem.get zip outer.imemNodes).foreach { case (coreMem, tileNode) =>
coreMem.d <> tileNode.out.head._1.d
coreMem.a <> tileNode.out.head._1.a
}
val arb = Module(new RRArbiter(core.io.dmem.head.d.bits.source.cloneType, 4))
val matchingSources = Wire(UInt(4.W))
val dmemDs = outer.dmemNodes.map(_.out.head._1.d)
val arb = Module(new RRArbiter(core.io.dmem.get.head.d.bits.source.cloneType, 4))
val matchingSources = Wire(UInt(4.W))
val dmemDs = outer.dmemNodes.map(_.out.head._1.d)
(arb.io.in zip dmemDs).zipWithIndex.foreach { case ((arbIn, tileNode), i) =>
arbIn.valid := tileNode.valid
arbIn.bits := tileNode.bits.source
// assert(arbIn.ready, "source id arbiter should always be ready")
}
matchingSources := dmemDs.map(d => (d.bits.source === arb.io.out.bits) && arb.io.out.valid).asUInt
arb.io.out.ready := true.B
(arb.io.in zip dmemDs).zipWithIndex.foreach { case ((arbIn, tileNode), i) =>
arbIn.valid := tileNode.valid
arbIn.bits := tileNode.bits.source
// assert(arbIn.ready, "source id arbiter should always be ready")
}
matchingSources := dmemDs.map(d => (d.bits.source === arb.io.out.bits) && arb.io.out.valid).asUInt
arb.io.out.ready := true.B
(core.io.dmem zip dmemDs).zipWithIndex.foreach { case ((coreMem, tileNode), i) =>
coreMem.d.bits := tileNode.bits
coreMem.d.valid := tileNode.valid && matchingSources(i)
tileNode.ready := coreMem.d.ready && matchingSources(i)
}
(core.io.dmem.get zip dmemDs).zipWithIndex.foreach { case ((coreMem, tileNode), i) =>
coreMem.d.bits := tileNode.bits
coreMem.d.valid := tileNode.valid && matchingSources(i)
tileNode.ready := coreMem.d.ready && matchingSources(i)
}
(core.io.dmem zip outer.dmemNodes).foreach { case (coreMem, tileNode) =>
coreMem.a <> tileNode.out.head._1.a
(core.io.dmem.get zip outer.dmemNodes).foreach { case (coreMem, tileNode) =>
coreMem.a <> tileNode.out.head._1.a
}
}
core.io.fpu := DontCare