L1 fatbank works with 2^5 source bits in SourceGen, failed with < 2^4 source bits in SourceGen
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Vamber Yang
@@ -73,6 +73,7 @@ class NewSourceGenerator[T <: Data](
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}
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when(io.reclaim.valid) {
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// @perf: would this require multiple write ports?
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assert(occupancyTable(io.reclaim.bits).id.valid === true.B, "tried to reclaim a non-used id")
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occupancyTable(io.reclaim.bits).id.valid := false.B // mark freed
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}
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io.peek := {
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@@ -104,7 +105,8 @@ case class VortexFatBankConfig(
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cacheLineSize: Int,
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coreTagWidth: Int,
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writeInfoReqQSize: Int,
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mshrSize: Int
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mshrSize: Int,
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uncachedAddrSets: Seq[AddressSet]
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) {
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def coreTagPlusSizeWidth: Int = {
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log2Ceil(wordSize) + coreTagWidth
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@@ -116,11 +118,12 @@ object defaultFatBankConfig extends VortexFatBankConfig(
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cacheLineSize = 16,
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coreTagWidth = 8,
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writeInfoReqQSize = 16,
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mshrSize = 8
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mshrSize = 8,
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uncachedAddrSets = Seq(AddressSet(0x2000000L, 0xFFL))
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)
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class VortexFatBank (config: VortexFatBankConfig) (implicit p: Parameters) extends LazyModule {
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class FatBankPassThrough(config:VortexFatBankConfig) (implicit p: Parameters) extends LazyModule {
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val clientParam = Seq(TLMasterPortParameters.v1(
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clients = Seq(
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@@ -139,7 +142,64 @@ class VortexFatBank (config: VortexFatBankConfig) (implicit p: Parameters) exten
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beatBytes = config.wordSize,
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managers = Seq(
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TLSlaveParameters.v1(
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address = Seq(AddressSet(0x80000000L, 0xfffffff)), // 0x80000000 -> 0x90000000 are possible address tracer can emit
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address = config.uncachedAddrSets,
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regionType = RegionType.IDEMPOTENT,
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executable = false,
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supportsGet = TransferSizes(1, config.wordSize),
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supportsPutPartial = TransferSizes(1, config.wordSize),
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supportsPutFull = TransferSizes(1, config.wordSize),
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fifoId = Some(0)
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)
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)
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))
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val coalToVxCacheNode = TLManagerNode(managerParam)
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val vxCacheFetchNode = TLClientNode(clientParam)
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val vxCacheToL2Node = TLIdentityNode()
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vxCacheToL2Node := TLWidthWidget(config.cacheLineSize) := vxCacheFetchNode
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//the implementation to make everything a pass through
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lazy val module = new LazyModuleImp(this) {
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val (upstream, _) = coalToVxCacheNode.in(0)
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val (downstream, _) = vxCacheFetchNode.out(0)
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downstream.a <> upstream.a
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upstream.d <> downstream.d
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}
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}
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class VortexFatBank (config: VortexFatBankConfig) (implicit p: Parameters) extends LazyModule {
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//Generate AddressSet by excluding Addr we don't want
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def generateAddressSets(excludeSets: Seq[AddressSet]): Seq[AddressSet] = {
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var remainingSets: Seq[AddressSet] = Seq(AddressSet(0x00000000L, 0xFFFFFFFFL))
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for(excludeSet <- excludeSets) {
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remainingSets = remainingSets.flatMap(_.subtract(excludeSet))
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}
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remainingSets
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}
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val clientParam = Seq(TLMasterPortParameters.v1(
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clients = Seq(
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TLMasterParameters.v1(
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name = "VortexFatBank",
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sourceId = IdRange(0, 1 << 14), // FIXME: magic number
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supportsProbe = TransferSizes(1, config.wordSize),
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supportsGet = TransferSizes(1, config.wordSize),
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supportsPutFull = TransferSizes(1, config.wordSize),
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supportsPutPartial = TransferSizes(1, config.wordSize)
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)
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)
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))
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val managerParam = Seq(TLSlavePortParameters.v1(
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beatBytes = config.wordSize,
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managers = Seq(
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TLSlaveParameters.v1(
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address = generateAddressSets(config.uncachedAddrSets),
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regionType = RegionType.IDEMPOTENT, // idk what this does
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executable = false,
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supportsGet = TransferSizes(1, config.wordSize),
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@@ -177,6 +237,24 @@ class VortexFatBankImp (
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vxCache.io.clk := clock
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vxCache.io.reset := reset
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val writeReqCount = RegInit(UInt(32.W), 0.U)
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val writeInputFire = Wire(Bool())
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val writeOutputFire = Wire(Bool())
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when(writeInputFire && ~writeOutputFire){
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writeReqCount := writeReqCount + 1.U
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}.elsewhen(~writeInputFire && writeOutputFire){
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writeReqCount := writeReqCount - 1.U
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}
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dontTouch(writeInputFire)
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dontTouch(writeOutputFire)
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dontTouch(writeReqCount)
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class WriteReqInfo extends Bundle {
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val id = UInt(32.W)
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val size = UInt(32.W)
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@@ -211,7 +289,8 @@ class VortexFatBankImp (
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readReqInfo.size := coalToBankA.bits.size
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vxCache.io.core_req_tag := readReqInfo.asTypeOf(vxCache.io.core_req_tag)
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writeInputFire := vxCache.io.core_req_rw && coalToBankA.fire
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// we ignore param, size, corrupt fields
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// vxCache -> coal response on channel D
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@@ -275,7 +354,7 @@ class VortexFatBankImp (
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//Therefore, we need our own internal source_ID generator for all write operation
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val sourceGen = Module( new NewSourceGenerator(log2Ceil(config.mshrSize), metadata = Some(UInt(32.W)), ignoreInUse = false))
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val sourceGen = Module( new NewSourceGenerator(3, metadata = Some(UInt(32.W)), ignoreInUse = false))
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@@ -288,10 +367,15 @@ class VortexFatBankImp (
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//Read Operation is ready as long as downstream L2 is ready
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vxCache.io.mem_req_ready := vxCacheToL2A.ready
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vxCache.io.mem_req_ready := vxCacheToL2A.ready && sourceGen.io.id.valid
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vxCacheToL2A.valid := vxCache.io.mem_req_valid && sourceGen.io.id.valid
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sourceGen.io.gen := vxCacheToL2A.fire
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writeOutputFire := vxCacheToL2A.fire && vxCache.io.mem_req_rw
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vxCacheToL2A.bits.opcode := Mux(
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vxCache.io.mem_req_rw,
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Mux(vxCache.io.mem_req_byteen.andR, TLMessages.PutFullData, TLMessages.PutPartialData),
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@@ -310,7 +394,6 @@ class VortexFatBankImp (
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vxCacheToL2A.bits.source := sourceGen.io.id.bits
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sourceGen.io.gen := vxCacheToL2A.ready && vxCacheToL2A.valid
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sourceGen.io.meta := vxCache.io.mem_req_tag //save the old read id
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vxCacheToL2A.bits.param := 0.U
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@@ -328,7 +411,7 @@ class VortexFatBankImp (
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vxCache.io.mem_rsp_data := vxCacheToL2D.bits.data
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// all ids needs to be reclaimed
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sourceGen.io.reclaim.valid := vxCacheToL2D.ready && vxCacheToL2D.valid
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sourceGen.io.reclaim.valid := vxCacheToL2D.fire
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sourceGen.io.reclaim.bits := vxCacheToL2D.bits.source
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}
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@@ -223,6 +223,27 @@ class VortexTile private (
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val coal = LazyModule(new CoalescingUnit(coalescerParam.copy(enable = true)))
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coal.cpuNode :=* dmemAggregateNode
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coal.aggregateNode // N+1 lanes
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//Conditionally instantiate fat-bank, we can only use fatbank in the presence of coalescer
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val coalFatbankNode = p(VortexFatBankKey) match {
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case Some(fatBankParam) =>{
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println(s"============ Using Vortex FatBank as L1 =================")
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val vx_fatbank = LazyModule(new VortexFatBank(fatBankParam))
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val passThrough = LazyModule(new FatBankPassThrough(fatBankParam))
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val coalXbar = LazyModule(new TLXbar)
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coalXbar.node :=* coal.aggregateNode
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vx_fatbank.coalToVxCacheNode :=* coalXbar.node
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passThrough.coalToVxCacheNode :=* coalXbar.node
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//merge these two into one identity node
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val fatBankSystem = TLIdentityNode()
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fatBankSystem := vx_fatbank.vxCacheToL2Node
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fatBankSystem := passThrough.vxCacheToL2Node
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fatBankSystem
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}
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case None => coal.aggregateNode //if no fatbank, simply return coalescer.aggregateNode
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}
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coalFatbankNode
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}
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case None => dmemAggregateNode
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}
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