VX_FatBank runs in SoC Config with Coalescer till termination
Issues addressed: 1. FatBank ack to downstream coalescer with the correct size on ChannelD 2. FatBank ack to downstream coalescer immediately after W Req 3. FatBank generates unique ID for W Req to L2 4. Allows coalescer to config max Coal to L1 ReadSize at compile time Ungoing issues: 1. Magic Number 2. Verification 3. Multi-Bank Integration
This commit is contained in:
Vamber Yang
@@ -1,4 +1,5 @@
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package rocket
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//package freechips.rocketchip.rocket
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package freechips.rocketchip.tilelink
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import chisel3._
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import chisel3.util._
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@@ -6,125 +7,261 @@ import chisel3.experimental._
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import org.chipsalliance.cde.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import org.chipsalliance.cde.config.{Parameters, Field}
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// VortexTile has dmemNodes, imemNodes
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class VortexFatBank (
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//Param and Key are used during SoC Generation
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) (implicit p: Parameters) extends LazyModule {
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case class VortexFatBankParam(wordSize: Int = 16, busWidthInBytes: Int = 8)
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case object VortexFatBankKey extends Field[Option[VortexFatBankConfig]](None /*default*/)
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case class VortexFatBankConfig(
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wordSize: Int, //This is the read/write granularity of the L1 cache
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cacheLineSize: Int,
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coreTagWidth: Int,
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) {
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def coreTagPlusSizeWidth: Int = {
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log2Ceil(wordSize) + coreTagWidth
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}
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}
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object defaultFatBankConfig extends VortexFatBankConfig(
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wordSize = 16,
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cacheLineSize = 16,
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coreTagWidth = 8,
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)
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class VortexFatBank (config: VortexFatBankConfig) (implicit p: Parameters) extends LazyModule {
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val clientParam = Seq(TLMasterPortParameters.v1(
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clients = Seq(
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TLMasterParameters.v1(
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name = "VortexFatBank",
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sourceId = IdRange(0, 1 << 14), // FIXME: magic number
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supportsProbe = TransferSizes(1, 16),
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supportsGet = TransferSizes(1, 16),
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supportsPutFull = TransferSizes(1, 16),
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supportsPutPartial = TransferSizes(1, 16)
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supportsProbe = TransferSizes(1, config.wordSize),
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supportsGet = TransferSizes(1, config.wordSize),
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supportsPutFull = TransferSizes(1, config.wordSize),
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supportsPutPartial = TransferSizes(1, config.wordSize)
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)
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)
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))
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val managerParam = Seq(TLSlavePortParameters.v1(
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beatBytes = 16,
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beatBytes = config.wordSize,
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managers = Seq(
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TLSlaveParameters.v1(
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address = Seq(AddressSet(0x0, 0xffffff)), // intercept all requests (it does not like all F for some reason)
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address = Seq(AddressSet(0x80000000L, 0xfffffff)), // 0x80000000 -> 0x90000000 are possible address tracer can emit
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regionType = RegionType.IDEMPOTENT, // idk what this does
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executable = false,
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supportsGet = TransferSizes(1, 16),
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supportsPutPartial = TransferSizes(1, 16),
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supportsPutFull = TransferSizes(1, 16),
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supportsGet = TransferSizes(1, config.wordSize),
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supportsPutPartial = TransferSizes(1, config.wordSize),
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supportsPutFull = TransferSizes(1, config.wordSize),
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fifoId = Some(0)
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)
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)
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))
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val coalToBankNode = TLManagerNode(managerParam)
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val bankToL2Node = TLClientNode(clientParam)
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lazy val module = new VortexFatBankImp(this);
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val coalToVxCacheNode = TLManagerNode(managerParam)
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val vxCacheToL2Node = TLIdentityNode()
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val vxCacheFetchNode = TLClientNode(clientParam)
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//We need this widthWidget here, because whenever the fatBank is performing
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//read and write to Mem, it must have the illusion that dataWidth is as big as
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//as its cacheline size
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vxCacheToL2Node := TLWidthWidget(config.cacheLineSize) := vxCacheFetchNode
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lazy val module = new VortexFatBankImp(this, config);
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}
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class VortexFatBankImp (
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outer: VortexFatBank
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outer: VortexFatBank,
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config: VortexFatBankConfig
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) extends LazyModuleImp(outer) {
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val bank = Module(new VX_Cache());
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bank.io.clk := clock
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bank.io.reset := reset
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val vxCache = Module(new VX_cache(
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WORD_SIZE=config.wordSize,
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CACHE_LINE_SIZE=config.cacheLineSize,
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CORE_TAG_WIDTH= config.coreTagPlusSizeWidth
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)
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);
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// Translate TL request from Coalescer to requests for VX_Cache
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vxCache.io.clk := clock
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vxCache.io.reset := reset
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class WriteReqInfo extends Bundle {
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val id = UInt(32.W)
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val size = UInt(32.W)
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}
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//<FIXME> assuming this is never full
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val rcvWriteReqInfo = Module(new Queue((new WriteReqInfo).cloneType, 64, true, false))
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class ReadReqInfo(config: VortexFatBankConfig) extends Bundle {
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val size = UInt(log2Ceil(config.wordSize).W)
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val id = UInt(config.coreTagWidth.W)
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}
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val readReqInfo = Wire(new ReadReqInfo(config))
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// Translate TL request from Coalescer to requests for VX_cache
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def TLReq2VXReq = {
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val (coalToBankBundle, _) = outer.coalToBankNode.in.head
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// coal -> bank request on channel A
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val (coalToBankBundle, _) = outer.coalToVxCacheNode.in.head
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// coal -> vxCache request on channel A
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val coalToBankA = coalToBankBundle.a;
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coalToBankA.ready := bank.io.core_req_ready
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bank.io.core_req_valid := coalToBankA.valid
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coalToBankA.ready := vxCache.io.core_req_ready
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vxCache.io.core_req_valid := coalToBankA.valid
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// read = 0, write = 1
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bank.io.core_req_rw := !(coalToBankA.bits.opcode === TLMessages.Get)
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bank.io.core_req_addr := coalToBankA.bits.address(31, 4)
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bank.io.core_req_byteen := coalToBankA.bits.mask
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bank.io.core_req_data := coalToBankA.bits.data
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bank.io.core_req_tag := coalToBankA.bits.source
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vxCache.io.core_req_rw := !(coalToBankA.bits.opcode === TLMessages.Get)
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//4 is also hardcoded, it should be log2WordSize
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vxCache.io.core_req_addr := coalToBankA.bits.address(31, 4)
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vxCache.io.core_req_byteen := coalToBankA.bits.mask
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vxCache.io.core_req_data := coalToBankA.bits.data
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readReqInfo.id := coalToBankA.bits.source
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readReqInfo.size := coalToBankA.bits.size
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vxCache.io.core_req_tag := readReqInfo.asTypeOf(vxCache.io.core_req_tag)
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// we ignore param, size, corrupt fields
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// bank -> coal response on channel D
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// vxCache -> coal response on channel D
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// ok ... this part is a little tricky, the downstream coalescer requires the L1 cache
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// to send ack and dataAck, this is how coalescer knows when an inflight ID has retired
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// if we don't send ack, the coalescer will run out of IDs, and can't generate new request
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// for read request, we send AckData when the FatBank has a valid output
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// for write request, we can immediate Ack on the next clock cycle (not the same clock cycle, otherwise critical path too long)
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// It's possible that on the same cycle, we need to do both "AckData" and "Ack"
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// in this case, we always priorize "Ack", this makes the design easier
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//I think this just shows the flaws of Tilelink. CPU never waits for an Ack upon regular write request
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//the Core should unconditionally move forward after every regular write request
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val coalToBankD = coalToBankBundle.d;
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bank.io.core_rsp_ready := coalToBankD.ready
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coalToBankD.valid := bank.io.core_rsp_valid
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// Cache is not TL compliant since we don't generate AccessAcks on successful writes
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// but VortexCore is not expecting them anyways
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coalToBankD.bits.opcode := TLMessages.AccessAckData
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//<FIXME> currently assuming below buffer is never full
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rcvWriteReqInfo.io.enq.valid := !(coalToBankA.bits.opcode === TLMessages.Get) && coalToBankA.valid && coalToBankA.ready
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rcvWriteReqInfo.io.enq.bits.id := coalToBankA.bits.source
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rcvWriteReqInfo.io.enq.bits.size := coalToBankA.bits.size
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rcvWriteReqInfo.io.deq.ready := coalToBankD.ready
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//if we "need" to do Ack
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//we unconditionally set the vxCache.ready to be false, so it gets delayed
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vxCache.io.core_rsp_ready := Mux(
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rcvWriteReqInfo.io.deq.valid,
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false.B,
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coalToBankD.ready
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)
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coalToBankD.valid := Mux(
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rcvWriteReqInfo.io.deq.valid,
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true.B,
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vxCache.io.core_rsp_valid
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)
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coalToBankD.bits.source := Mux(
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rcvWriteReqInfo.io.deq.valid,
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rcvWriteReqInfo.io.deq.bits.id,
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vxCache.io.core_rsp_tag.asTypeOf(readReqInfo).id
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)
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coalToBankD.bits.opcode := Mux(
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rcvWriteReqInfo.io.deq.valid,
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TLMessages.AccessAck,
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TLMessages.AccessAckData
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)
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coalToBankD.bits.size := Mux(
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rcvWriteReqInfo.io.deq.valid,
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rcvWriteReqInfo.io.deq.bits.size,
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vxCache.io.core_rsp_tag.asTypeOf(readReqInfo).size
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)
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coalToBankD.bits.param := 0.U
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coalToBankD.bits.size := 4.U
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coalToBankD.bits.sink := 0.U
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coalToBankD.bits.denied := false.B
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coalToBankD.bits.corrupt := false.B
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coalToBankD.bits.data := bank.io.core_rsp_data
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coalToBankD.bits.source := bank.io.core_rsp_tag
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coalToBankD.bits.data := vxCache.io.core_rsp_data
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}
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// Translate VX_Cache mem request to a TL request to be sent to L2
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//Using Hansung's Source Generator
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//Why do we need to do this, what is the issue ?
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//Tilelink requires all inflight Read and Write Request to have a unique source_ID
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//vx_cache can indeed guarantee that all active read operation has unique ID
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//However, since the cache is write_through, so it can't ensure unique ID for write operation
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//Therefore, we need our own internal source_ID generator for all write operation
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//
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//Now, we allocate id range: 0-15 for all write operation
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// and 16-> above for read operation
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val sourceGen = Module( new SourceGenerator(log2Ceil(16), ignoreInUse = false))
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// Translate VX_cache mem request to a TL request to be sent to L2
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def VXReq2TLReq = {
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val (bankToL2Bundle, _) = outer.bankToL2Node.out.head
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// bank -> L2 request on channel A
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val bankToL2A = bankToL2Bundle.a;
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val (vxCacheToL2Bundle, _) = outer.vxCacheFetchNode.out.head
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// vxCache -> L2 request on channel A
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val vxCacheToL2A = vxCacheToL2Bundle.a;
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bank.io.mem_req_ready := bankToL2A.ready
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bankToL2A.valid := bank.io.mem_req_valid
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//Read Operation is ready as long as downstream L2 is ready
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bankToL2A.bits.opcode := Mux(
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bank.io.mem_req_rw,
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Mux(bank.io.mem_req_byteen.andR, TLMessages.PutFullData, TLMessages.PutPartialData),
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vxCache.io.mem_req_ready := vxCacheToL2A.ready
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vxCacheToL2A.valid := Mux(
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vxCache.io.mem_req_rw,
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vxCache.io.mem_req_valid && sourceGen.io.id.valid,
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vxCache.io.mem_req_valid
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)
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vxCacheToL2A.bits.opcode := Mux(
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vxCache.io.mem_req_rw,
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Mux(vxCache.io.mem_req_byteen.andR, TLMessages.PutFullData, TLMessages.PutPartialData),
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TLMessages.Get
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)
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bankToL2A.bits.address := Cat(bank.io.mem_req_addr, 0.U(4.W))
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bankToL2A.bits.mask := bank.io.mem_req_byteen
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bankToL2A.bits.data := bank.io.mem_req_data
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bankToL2A.bits.source := bank.io.mem_req_tag
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bankToL2A.bits.param := 0.U
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bankToL2A.bits.size := 4.U
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bankToL2A.bits.corrupt := false.B
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vxCacheToL2A.bits.address := Cat(vxCache.io.mem_req_addr, 0.U(4.W))
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vxCacheToL2A.bits.mask := Mux(
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vxCache.io.mem_req_rw,
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vxCache.io.mem_req_byteen,
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0xFFFF.U
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)
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vxCacheToL2A.bits.data := vxCache.io.mem_req_data
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vxCacheToL2A.bits.source := Mux(
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vxCache.io.mem_req_rw,
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sourceGen.io.id.bits,
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vxCache.io.mem_req_tag + 16.U
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)
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//mark current source_id as in-use
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sourceGen.io.gen := vxCache.io.mem_req_rw && vxCacheToL2A.ready && vxCacheToL2A.valid
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vxCacheToL2A.bits.param := 0.U
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vxCacheToL2A.bits.size := 4.U
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vxCacheToL2A.bits.corrupt := false.B
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// we ignore param, size, corrupt fields
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// L2 -> bank response on channel D
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val bankToL2D = bankToL2Bundle.d;
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// L2 -> vxCache response on channel D
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val vxCacheToL2D = vxCacheToL2Bundle.d;
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vxCacheToL2D.ready := vxCache.io.mem_rsp_ready
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bankToL2D.ready := bank.io.mem_rsp_ready
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bank.io.mem_rsp_valid := (bankToL2D.valid && (bankToL2D.bits.opcode === TLMessages.AccessAckData)) // need to ignore AccessAcks
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vxCache.io.mem_rsp_valid := vxCacheToL2D.valid && vxCacheToL2D.bits.opcode === TLMessages.AccessAckData
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vxCache.io.mem_rsp_tag := vxCacheToL2D.bits.source - 16.U // -16 for read resp, we can safely do this, since write-ack wouldn't pass through
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vxCache.io.mem_rsp_data := vxCacheToL2D.bits.data
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bank.io.mem_rsp_tag := bankToL2D.bits.source
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bank.io.mem_rsp_data := bankToL2D.bits.data
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sourceGen.io.reclaim.valid := vxCacheToL2D.ready && vxCacheToL2D.valid && vxCacheToL2D.bits.opcode === TLMessages.AccessAck
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sourceGen.io.reclaim.bits := vxCacheToL2D.bits.source
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}
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@@ -133,7 +270,7 @@ class VortexFatBankImp (
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}
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class VX_Cache (
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class VX_cache (
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CACHE_ID: Int = 0,
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CACHE_SIZE: Int = 16384,
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CACHE_LINE_SIZE: Int = 16,
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@@ -145,10 +282,10 @@ class VX_Cache (
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MRSQ_SIZE: Int = 0,
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MREQ_SIZE: Int = 4,
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WRITE_ENABLE: Int = 1,
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CORE_TAG_WIDTH: Int = 10, // source ID ranges from 0 to 1 << 10
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CORE_TAG_WIDTH: Int = 10, // source ID ranges from 0 to 1 << 10, we need to allocate upper bits to save size
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CORE_TAG_ID_BITS: Int = 5, // no idea what this is, just match it with default L1 dcache
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BANK_ADDR_OFFSET: Int = 0,
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NC_ENABLE: Int = 1, // Unsure what this does, but it's elaborated as 1 in default L1 setup so hopefully this is ok
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NC_ENABLE: Int = 0, //NC_ENABLE=1 means the cache becomes a passthrough
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WORD_ADDR_WIDTH: Int = 28, // 16 byte "word" = 4 bits
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MEM_TAG_WIDTH: Int = 14, // Elaborated value is also completely different from (32 - log2Ceil(CACHE_LINE_SIZE)). This should match with sourceIds on client node associated with this cache
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MEM_ADDR_WIDTH: Int = 28 // 16 byte cache line = 4 bits
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@@ -210,8 +347,33 @@ class VX_Cache (
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val mem_rsp_ready = Output(Bool())
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})
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addResource("/vsrc/vortex/hw/rtl/VX_dispatch.sv")
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addResource("/vsrc/vortex/hw/rtl/VX_issue.sv")
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addResource("/vsrc/vortex/hw/rtl/cache/VX_cache_define.vh")
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// unused addResource("/vsrc/vortex/hw/rtl/libs/VX_mux.sv")
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addResource("/vsrc/vortex/hw/rtl/VX_warp_sched.sv")
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addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_sat.sv")
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addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_stride.sv")
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addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_lerp.sv")
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addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_addr.sv")
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addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_mem.sv")
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addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_format.sv")
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addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_sampler.sv")
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addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_unit.sv")
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addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_define.vh")
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addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_wrap.sv")
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addResource("/vsrc/vortex/hw/rtl/VX_scope.vh")
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addResource("/vsrc/vortex/hw/rtl/VX_fpu_unit.sv")
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addResource("/vsrc/vortex/hw/rtl/VX_scoreboard.sv")
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addResource("/vsrc/vortex/hw/rtl/VX_writeback.sv")
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addResource("/vsrc/vortex/hw/rtl/VX_muldiv.sv")
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addResource("/vsrc/vortex/hw/rtl/VX_decode.sv")
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addResource("/vsrc/vortex/hw/rtl/VX_ibuffer.sv")
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addResource("/vsrc/vortex/hw/rtl/VX_icache_stage.sv")
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addResource("/vsrc/vortex/hw/rtl/VX_gpu_unit.sv")
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addResource("/vsrc/vortex/hw/rtl/VX_trace_instr.vh")
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addResource("/vsrc/vortex/hw/rtl/VX_gpu_types.vh")
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addResource("/vsrc/vortex/hw/rtl/VX_config.vh")
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addResource("/vsrc/vortex/hw/rtl/libs/VX_lzc.sv")
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addResource("/vsrc/vortex/hw/rtl/libs/VX_fifo_queue.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/libs/VX_scan.sv")
|
||||
@@ -219,7 +381,6 @@ class VX_Cache (
|
||||
addResource("/vsrc/vortex/hw/rtl/libs/VX_multiplier.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/libs/VX_bits_remove.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/libs/VX_pipe_register.sv")
|
||||
// unused addResource("/vsrc/vortex/hw/rtl/libs/VX_onehot_mux.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/libs/VX_priority_encoder.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/libs/VX_reset_relay.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/libs/VX_popcount.sv")
|
||||
@@ -230,36 +391,80 @@ class VX_Cache (
|
||||
addResource("/vsrc/vortex/hw/rtl/libs/VX_index_buffer.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/libs/VX_onehot_encoder.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/libs/VX_matrix_arbiter.sv")
|
||||
// unused addResource("/vsrc/vortex/hw/rtl/libs/VX_divider.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/libs/VX_dp_ram.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/libs/VX_axi_adapter.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/libs/VX_elastic_buffer.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/libs/VX_rr_arbiter.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/libs/VX_stream_arbiter.sv")
|
||||
// unused addResource("/vsrc/vortex/hw/rtl/libs/VX_bypass_buffer.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/libs/VX_sp_ram.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/libs/VX_stream_demux.sv")
|
||||
|
||||
// unused addResource("/vsrc/vortex/hw/rtl/libs/VX_index_queue.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/libs/VX_serial_div.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/libs/VX_fair_arbiter.sv")
|
||||
|
||||
addResource("/vsrc/vortex/hw/rtl/libs/VX_pending_size.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/VX_define.vh")
|
||||
addResource("/vsrc/vortex/hw/rtl/VX_csr_data.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/VX_cache_arb.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/VX_ipdom_stack.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/VX_gpr_stage.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/VX_execute.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/VX_fetch.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/VX_alu_unit.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/VX_platform.vh")
|
||||
addResource("/vsrc/vortex/hw/rtl/VX_commit.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/VX_pipeline.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/VX_lsu_unit.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/VX_csr_unit.sv")
|
||||
addResource("/vsrc/vortex/hw/VX_config.h")
|
||||
|
||||
addResource("/vsrc/vortex/sim/common/rvfloats.h")
|
||||
addResource("/vsrc/vortex/sim/common/rvfloats.cpp")
|
||||
addResource("/csrc/softfloat/include/internals.h")
|
||||
addResource("/csrc/softfloat/include/primitives.h")
|
||||
addResource("/csrc/softfloat/include/primitiveTypes.h")
|
||||
addResource("/csrc/softfloat/include/softfloat.h")
|
||||
addResource("/csrc/softfloat/include/softfloat_types.h")
|
||||
addResource("/csrc/softfloat/RISCV/specialize.h")
|
||||
addResource("/vsrc/vortex/hw/dpi/float_dpi.cpp")
|
||||
addResource("/vsrc/vortex/hw/dpi/float_dpi.vh")
|
||||
addResource("/vsrc/vortex/hw/dpi/util_dpi.cpp")
|
||||
addResource("/vsrc/vortex/hw/dpi/util_dpi.vh")
|
||||
addResource("/vsrc/vortex/hw/rtl/fp_cores/VX_fpu_dpi.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/fp_cores/VX_fpu_define.vh")
|
||||
addResource("/vsrc/vortex/hw/rtl/fp_cores/VX_fpu_types.vh")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_icache_rsp_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_dcache_req_if.sv")
|
||||
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_tex_csr_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_join_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_ifetch_req_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_perf_cache_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_perf_memsys_if.sv")
|
||||
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_gpr_req_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_decode_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_writeback_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_gpu_req_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_perf_pipeline_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_gpr_rsp_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_cmt_to_csr_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_csr_to_alu_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_ifetch_rsp_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_alu_req_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_csr_req_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_ibuffer_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_branch_ctl_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_dcache_rsp_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_icache_req_if.sv")
|
||||
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_lsu_req_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_wstall_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_mem_rsp_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_fpu_to_csr_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_commit_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_tex_req_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_warp_ctl_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_tex_rsp_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_fetch_to_csr_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_perf_tex_if.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_mem_req_if.sv")
|
||||
|
||||
addResource("/vsrc/vortex/hw/rtl/cache/VX_shared_mem.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_fpu_req_if.sv")
|
||||
//addResource("/vsrc/vortex/hw/rtl/cache/VX_shared_mem.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/cache/VX_core_rsp_merge.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/cache/VX_tag_access.sv")
|
||||
addResource("/vsrc/vortex/hw/rtl/cache/VX_core_req_bank_sel.sv")
|
||||
|
||||
@@ -3,6 +3,8 @@ package freechips.rocketchip.tilelink
|
||||
import freechips.rocketchip.diplomacy.LazyModule
|
||||
import freechips.rocketchip.subsystem.BaseSubsystem
|
||||
import org.chipsalliance.cde.config.Parameters
|
||||
import freechips.rocketchip.rocket
|
||||
|
||||
|
||||
// TODO: possibly move to somewhere closer to CoalescingUnit
|
||||
// TODO: separate coalescer config from CanHaveMemtraceCore
|
||||
@@ -44,16 +46,39 @@ trait CanHaveMemtraceCore { this: BaseSubsystem =>
|
||||
}
|
||||
case None => tracer.node
|
||||
}
|
||||
val upstream = p(CoalXbarKey) match {
|
||||
val coalXbar = p(CoalXbarKey) match {
|
||||
case Some(xbarParam) =>{
|
||||
val priorityXbar = LazyModule(new CoalescerTLPriortyXBar)
|
||||
println(s"============ Using Priority XBar for Coalescer Requests ")
|
||||
priorityXbar.node :=* coalescerNode
|
||||
priorityXbar.node
|
||||
val coXbar = LazyModule(new TLXbar)
|
||||
println(s"============ Using TLXBar for Coalescer Requests ")
|
||||
coXbar.node :=* coalescerNode
|
||||
coXbar.node
|
||||
}
|
||||
case None => coalescerNode
|
||||
}
|
||||
|
||||
val vortexBank = p(VortexFatBankKey) match {
|
||||
case Some(fatBankParam) =>{
|
||||
val vx_fatbank = LazyModule(new VortexFatBank(fatBankParam))
|
||||
println(s"============ Using Vortex FatBank as L1 ")
|
||||
vx_fatbank.coalToVxCacheNode :=* coalXbar
|
||||
vx_fatbank.vxCacheToL2Node
|
||||
}
|
||||
case None => coalXbar
|
||||
}
|
||||
|
||||
|
||||
//If there is only 1 bank, the code below is useless
|
||||
val upstream = p(CoalXbarKey) match {
|
||||
case Some(xbarParam) =>{
|
||||
val tileXbar = LazyModule(new TLXbar)
|
||||
println(s"============ Using TLXBar for L1 Requests ")
|
||||
tileXbar.node :=* vortexBank
|
||||
tileXbar.node
|
||||
}
|
||||
case None => vortexBank
|
||||
}
|
||||
|
||||
|
||||
sbus.coupleFrom(s"gpu-tracer") { _ :=* upstream }
|
||||
}
|
||||
}
|
||||
|
||||
@@ -774,6 +774,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig)
|
||||
println(s" numNewSrcIds: ${config.numNewSrcIds}")
|
||||
println(s" reqQueueDepth: ${config.queueDepth}")
|
||||
println(s" respQueueDepth: ${config.respQueueDepth}")
|
||||
println(s" addressWidth: ${config.addressWidth}")
|
||||
println(s"}")
|
||||
|
||||
require(
|
||||
|
||||
Reference in New Issue
Block a user