Fix matchingSources logic when all lanes are invalid

When all lanes are invalid so that arb.io.valid is 0, we should not
deassert d_ready.

src/main/scala/tile/VortexTile.scala

@@ -216,7 +216,7 @@ class VortexTile private (
   // Conditionally instantiate memory coalescer
   val coalescerNode = p(CoalescerKey) match {
     case Some(coalescerParam) => {
-      val coal = LazyModule(new CoalescingUnit(coalescerParam))
+      val coal = LazyModule(new CoalescingUnit(coalescerParam.copy(enable = false)))
       coal.cpuNode :=* dmemAggregateNode
       coal.aggregateNode // N+1 lanes
     }
@@ -406,7 +406,12 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
     }
     val matchingSources = Wire(UInt(outer.numLanes.W))
     matchingSources := dmemTLBundles
-      .map(b => (b.d.bits.source === arb.io.out.bits) && arb.io.out.valid)
+      .map(b =>
+          // If there is no valid response across all lanes, matchingSources
+          // should always be 1, or otherwise downstream would think upstream
+          // is blocked and re-try sending
+          !arb.io.out.valid
+          || (b.d.bits.source === arb.io.out.bits))
       .asUInt
 
     // connection: VortexBundle <--> VortexTLAdapter <--> dmemNodes
@@ -438,6 +443,11 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
         tlAdapter.io.outResp.valid := tlBundle.d.valid && matchingSources(i)
         tlBundle.d.ready := tlAdapter.io.outResp.ready && matchingSources(i)
     }
+
+    outer.dmemAggregateNode.out.foreach { bo =>
+      dontTouch(bo._1.a)
+      dontTouch(bo._1.d)
+    }
   }
 
   // TODO: generalize for useVxCache

src/main/scala/tilelink/Coalescing.scala

@@ -102,7 +102,7 @@ case class CoalescerConfig(
 object DefaultCoalescerConfig extends CoalescerConfig(
   enable = true,
   numLanes = 4,
-  queueDepth = 1,
+  queueDepth = 1, // 1-deep request queues
   waitTimeout = 8,
   addressWidth = 24,
   dataBusWidth = 4,      // if "4": 2^4=16 bytes, 128 bit bus