Use VortexTLAdapter for useVxCache = true as well
This commit is contained in:
Hansung Kim
@@ -10,20 +10,28 @@ import org.chipsalliance.cde.config.Parameters
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import freechips.rocketchip.tile._
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import tile.VortexTile
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class VortexBundleA extends Bundle {
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class VortexBundleA(
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sourceWidth: Int,
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dataWidth: Int
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) extends Bundle {
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assert(dataWidth % 8 == 0)
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val opcode = UInt(3.W) // FIXME: hardcoded
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val size = UInt(4.W) // FIXME: hardcoded
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val source = UInt(10.W) // FIXME: hardcoded
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val source = UInt(sourceWidth.W) // FIXME: hardcoded
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val address = UInt(32.W) // FIXME: hardcoded
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val mask = UInt(4.W) // FIXME: hardcoded
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val data = UInt(32.W) // FIXME: hardcoded
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val mask = UInt((dataWidth / 8).W) // FIXME: hardcoded
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val data = UInt(dataWidth.W) // FIXME: hardcoded
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}
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class VortexBundleD extends Bundle {
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class VortexBundleD(
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sourceWidth: Int,
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dataWidth: Int
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) extends Bundle {
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assert(dataWidth % 8 == 0)
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val opcode = UInt(3.W) // FIXME: hardcoded
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val size = UInt(4.W) // FIXME: hardcoded
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val source = UInt(10.W) // FIXME: hardcoded
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val data = UInt(32.W) // FIXME: hardcoded
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val source = UInt(sourceWidth.W) // FIXME: hardcoded
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val data = UInt(dataWidth.W) // FIXME: hardcoded
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}
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class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle {
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@@ -35,16 +43,18 @@ class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle
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// conditionally instantiate ports depending on whether we want to use VX_cache or not
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val imem = if (!tile.vortexParams.useVxCache) Some(Vec(1, new Bundle {
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val a = Decoupled(new VortexBundleA())
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val d = Flipped(Decoupled(new VortexBundleD()))
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val a = Decoupled(new VortexBundleA(sourceWidth = 10, dataWidth = 32))
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val d = Flipped(Decoupled(new VortexBundleD(sourceWidth = 10, dataWidth = 32)))
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})) else None
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val dmem = if (!tile.vortexParams.useVxCache) Some(Vec(tile.numLanes, new Bundle {
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val a = Decoupled(new VortexBundleA())
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val d = Flipped(Decoupled(new VortexBundleD()))
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val a = Decoupled(new VortexBundleA(sourceWidth = 10, dataWidth = 32))
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val d = Flipped(Decoupled(new VortexBundleD(sourceWidth = 10, dataWidth = 32)))
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})) else None
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val mem = if (tile.vortexParams.useVxCache) Some(new Bundle {
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val a = tile.memNode.out.head._1.a.cloneType
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val d = Flipped(tile.memNode.out.head._1.d.cloneType)
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val a = Decoupled(new VortexBundleA(sourceWidth = 15, dataWidth = 128))
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val d = Flipped(Decoupled(new VortexBundleD(sourceWidth = 15, dataWidth = 128)))
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// val a = tile.memNode.out.head._1.a.cloneType
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// val d = Flipped(tile.memNode.out.head._1.d.cloneType)
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}) else None
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// val fpu = Flipped(new FPUCoreIO())
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@@ -135,15 +135,16 @@ class VortexTile private (
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)
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}
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println(s"============= lazyCoreParamsView.coreDataBytes=${lazyCoreParamsView.coreDataBytes}")
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val memNode = TLClientNode(
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Seq(
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TLMasterPortParameters.v1(
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clients = Seq(
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TLMasterParameters.v1(
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sourceId = IdRange(0, 1 << 15), // TODO magic numbers
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sourceId = IdRange(0, 1 << sourceWidth),
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name = s"Vortex Core ${vortexParams.hartId} Mem Interface",
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requestFifo = true,
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supportsProbe = TransferSizes(16, 16),
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supportsProbe = TransferSizes(16, 16), // FIXME: hardcoded
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supportsGet = TransferSizes(16, 16),
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supportsPutFull = TransferSizes(16, 16),
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supportsPutPartial = TransferSizes(16, 16)
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@@ -284,16 +285,35 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
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// require(core.io.hartid.getWidth >= outer.hartIdSinkNode.bundle.getWidth,
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// s"core hartid wire (${core.io.hartid.getWidth}b) truncates external hartid wire (${outer.hartIdSinkNode.bundle.getWidth}b)")
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// ---------------------------------------------
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// Translate Vortex memory interface to TileLink
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// ---------------------------------------------
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if (outer.vortexParams.useVxCache) {
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println(s"width of a channel data ${core.io.mem.get.a.bits.data.getWidth}")
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println(s"width of d channel data ${core.io.mem.get.d.bits.data.getWidth}")
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core.io.mem.get.a <> outer.memNode.out.head._1.a
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core.io.mem.get.d <> outer.memNode.out.head._1.d
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val memTLAdapter = Module(new VortexTLAdapter(
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outer.sourceWidth,
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chiselTypeOf(core.io.mem.get.a.bits),
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chiselTypeOf(core.io.mem.get.d.bits),
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chiselTypeOf(outer.memNode.out.head._1.a.bits),
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chiselTypeOf(outer.memNode.out.head._1.d.bits),
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))
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// connection: VortexBundle <--> VortexTLAdapter <--> TL memNode
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memTLAdapter.io.inReq <> core.io.mem.get.a
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core.io.mem.get.d <> memTLAdapter.io.inResp
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outer.memNode.out(0)._1.a <> memTLAdapter.io.outReq
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memTLAdapter.io.outResp <> outer.memNode.out(0)._1.d
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// core.io.mem.get.a <> outer.memNode.out.head._1.a
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// core.io.mem.get.d <> outer.memNode.out.head._1.d
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} else {
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val imemTLAdapter = Module(new VortexTLAdapter(
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outer.sourceWidth,
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new VortexBundleA(),
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new VortexBundleD(),
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chiselTypeOf(core.io.imem.get(0).a.bits),
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chiselTypeOf(core.io.imem.get(0).d.bits),
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chiselTypeOf(outer.imemNodes.head.out.head._1.a.bits),
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chiselTypeOf(outer.imemNodes.head.out.head._1.d.bits),
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))
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@@ -326,26 +346,26 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
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// connection: VortexBundle <--> VortexTLAdapter <--> dmemNodes
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// @perf: this would duplicate SourceGenerator table for every lane and eat
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// up some area
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val tlAdapters = Seq.tabulate(outer.numLanes) { _ =>
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val dmemTLAdapters = Seq.tabulate(outer.numLanes) { _ =>
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Module(new VortexTLAdapter(
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outer.sourceWidth,
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new VortexBundleA(),
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new VortexBundleD(),
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chiselTypeOf(core.io.dmem.get(0).a.bits),
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chiselTypeOf(core.io.dmem.get(0).d.bits),
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chiselTypeOf(dmemTLBundles.head.a.bits),
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chiselTypeOf(dmemTLBundles.head.d.bits),
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))
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}
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(core.io.dmem.get zip tlAdapters) foreach { case (coreMem, tlAdapter) =>
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(core.io.dmem.get zip dmemTLAdapters) foreach { case (coreMem, tlAdapter) =>
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tlAdapter.io.inReq <> coreMem.a
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coreMem.d <> tlAdapter.io.inResp
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}
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(tlAdapters zip dmemTLBundles) foreach { case (tlAdapter, tlBundle) =>
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(dmemTLAdapters zip dmemTLBundles) foreach { case (tlAdapter, tlBundle) =>
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tlBundle.a <> tlAdapter.io.outReq
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}
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// using the chosen source id,
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// - lie to core that response is not valid if source doesn't match picked
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// - lie to downstream that core is not ready if source doesn't match picked
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(tlAdapters zip dmemTLBundles).zipWithIndex.foreach {
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(dmemTLAdapters zip dmemTLBundles).zipWithIndex.foreach {
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case ((tlAdapter, tlBundle), i) =>
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tlAdapter.io.outResp.bits := tlBundle.d.bits
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tlAdapter.io.outResp.valid := tlBundle.d.valid && matchingSources(i)
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