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Author SHA1 Message Date
Hansung Kim
8a7e6f1391 Replace hardcoded trace widths with proper params 2023-04-21 18:20:16 -07:00
Hansung Kim
bbe62a8583 Properly count per-lane req/resps 2023-04-21 17:24:43 -07:00
Hansung Kim
db06bda674 Count req/resp lines and bytes to coalescer and test match 
Note total bytes in requests and responses (i.e. traffic) don't
need to match because of redundant requests to the same address may get
coalesced.
 2023-04-21 16:49:19 -07:00
Hansung Kim
3ba566b9f7 Give slack time after trace EOF before sim termination 
... so that we make sure to receive all outstanding responses.
This fixes the response traces being truncated too early.
 2023-04-21 16:27:20 -07:00
Hansung Kim
3f9f7a1d67 Generate proper AccessAck/AccessAckData from response queue 2023-04-21 16:14:52 -07:00
Hansung Kim
e04ffe2130 Generate separate traces per logger/req/resp 2023-04-21 15:53:15 -07:00
Hansung Kim
6ae08b6541 Add missing sizeWidth to uncoalescer test 2023-04-21 11:24:57 -07:00
Hansung Kim
de478dcca9 Generate both Put/Get for non-coalesced requests 2023-04-20 21:57:40 -07:00
Hansung Kim
a9719d5e36 Split tl*OpcodeIsStore out to global scope 2023-04-20 21:42:56 -07:00
Hansung Kim
de6d6eee1a Fix request shift queue not enqueuing when empty 
The queue was enabling shifting of the registers whenever deq.ready
was 1, even when the queue was empty.  This caused `wen` to disable
writing enq.bits to any of the entries in the queue.  Fixed by setting
`shift` to 0 when queue is empty.
 2023-04-20 21:12:19 -07:00
Hansung Kim
7e405b5355 Re-enable coalescer in TLRAMCoalescerLoggerTest 
Now that the driver and logger are working (kinda).
 2023-04-20 21:11:12 -07:00
Hansung Kim
b2ab45f5e2 Change parameters to spatial-only coalescing 2023-04-20 21:09:19 -07:00
Hansung Kim
322f340657 Manage to make new bugs while doing that 2023-04-18 00:14:33 -07:00
Hansung Kim
65a22b7fcb Use TLMessages constants instead of numbers 2023-04-18 00:09:48 -07:00
Hansung Kim
2ac5ee398a Doc 2023-04-17 21:31:13 -07:00
Hansung Kim
334d05b222 Remove leftover printf 2023-04-17 21:17:23 -07:00
Hansung Kim
02ce969c67 Fix width mismatch for source logger 2023-04-17 18:52:38 -07:00
Hansung Kim
d4a51cfee5 Log source ID in the trace 2023-04-17 18:43:17 -07:00
Hansung Kim
41d520a991 Log both request and response in trace logger 
Inside DPI code, have a vector of unique_ptrs that act as handles to multiple
different trace logger instances.  Each logger instance is instantiated in a
single instance of the Verilog module, and multiple of these Verilog modules may
be instantiated in the Chisel module (see simReq and simResp in MemTraceLogger).
 2023-04-17 18:10:13 -07:00
Hansung Kim
8978c2a812 trait HasTraceReq 2023-04-17 16:51:37 -07:00
Hansung Kim
f60602fc34 Write trace from logger in the same format as driver 2023-04-17 16:26:25 -07:00
Hansung Kim
282434eb7d Basic C++ file IO for trace logger 2023-04-17 16:20:27 -07:00
Hansung Kim
1a90ad52ac Cleanup tracer debug prints 2023-04-17 15:50:46 -07:00
Hansung Kim
8e6a5f4bce Fix address & data handling in memtrace driver and logger 
* TileLink doesn't alter the `address` field from what we originally used in the
  Get/Put call.
* Same goes for the `data` field.
* The only thing TL generates by itself is `mask`.  This means we have to align
  data to the beatBytes boundary ourselves when Putting, and also taking
  the right sublanes using the mask when Getting.
 2023-04-17 15:30:30 -07:00
Hansung Kim
57874a564e Set TL size according to trace from driver 
Mask will be set accordingly by the TL generator methods (Get/Put).
 2023-04-12 14:23:17 -07:00
Hansung Kim
8e763b512a Relay full trace line info to DPI 2023-04-12 13:54:59 -07:00
Hansung Kim
1057ed59d3 Parse log2(size) from trace; set is_store from TL opcode 2023-04-11 18:23:50 -07:00
Hansung Kim
71f334bb22 Fix size parsing from memtrace 2023-04-11 17:36:45 -07:00
Hansung Kim
62f940618e Convert manual bitshift to Chisel bitfield access 2023-04-10 21:04:04 -07:00
Hansung Kim
dca52ace0b Fix verilog lint error 2023-04-10 20:37:26 -07:00
Hansung Kim
b53711965e Connect TL edge data to SimMemTraceLogger 
TODO: since TileLink rounds all address down to a multiple of its beat
size (8 in the current code), we can't directly compare the memory trace
input to its output.  Need to take masks into account.
 2023-04-10 20:24:27 -07:00
Hansung Kim
af29acdcda Placeholder for MemTraceLogger C++ code 2023-04-09 14:53:02 -07:00
Hansung Kim
452cc40eb7 Make MemTraceLogger pass-through node 
Instead of making MemTraceLogger a TL slave, make it an IdentityNode
that simply snoops on the TL edges and generates logs.
We can attach a TLRAM at the downstream to actually get response back,
rather than MemTraceLogger simply absorbing all requests.
 2023-04-07 17:22:52 -07:00
Hansung Kim
109ad2cac0 Write MemTraceLogger and new synthesizable unittest 2023-04-07 16:23:14 -07:00
Hansung Kim
abecd30b2b Store sourceId for every old req entry in table 2023-04-07 14:50:40 -07:00
Vamber Yang
8e5254292b Attach MemTracer to SBus , all physical addr hashed between 0X80000000->0X90000000 2023-04-05 23:43:22 -07:00
Hansung Kim
bdc32b765f Accept memory trace filename from VCS plusargs 
Now can use `EXTRA_SIM_FLAGS="+memtracefile=<tracefile>"` to simulate
with different trace files without recompiling.
 2023-04-03 17:41:47 -07:00
Hansung Kim
c0d502960f Experiment with coalescing across all lanes 2023-04-02 12:23:28 -07:00
Hansung Kim
d62732fb89 Invalidate outgoing per-lane requests that got coalesced 
Now the response queue no longer blocks the flow!
 2023-04-01 14:33:46 -07:00
Hansung Kim
d9f6e27a04 Move coalescer chiseltest to its own package 2023-03-31 20:51:34 -07:00
Hansung Kim
4aabbecda1 Do not deassert deq.valid right after invalidate(head) 
... to avoid combinational cycle.
 2023-03-31 20:40:12 -07:00
Hansung Kim
1c0c8fa112 Complete test for enqueuing to invalidated tail 2023-03-31 20:15:49 -07:00
Hansung Kim
92ad5c2548 Cleanup padding logic 2023-03-31 20:12:43 -07:00
Hansung Kim
3ee639f376 Eliminate unnecessary delay when invalidating head 
When invalidate signal is given for queue head, that head should be
gone immediately at the next cycle, regardless of what deq.ready was
at the previous cycle.
 2023-03-31 19:55:36 -07:00
Hansung Kim
6ca22a39e0 Implement automatic dequeuing of invalid entries 2023-03-31 19:40:10 -07:00
Hansung Kim
f44dfc8d5a Implement invalidation for the queue 2023-03-31 19:25:45 -07:00
Hansung Kim
a0d75530cb Use used mask in CoalShiftQueue 
Easier to use than wptr when enqueuing & dequeueing at the same time.
 2023-03-31 17:10:09 -07:00
Hansung Kim
303c43a5e2 Make CoalShiftQueue use wptr; add unit test 
Cannot solely rely on valid mask because there may be holes in the
middle.
 2023-03-29 19:06:08 -07:00
Hansung Kim
a3472752bf Duplicate ShiftQueue definition to make entries visible 2023-03-29 16:06:14 -07:00
Hansung Kim
12b3b67687 Store multiple oldSrcId reqs per lane in a table row 
The number of the per-lane reqs is controlled by `numPerLaneReqs`
rather than being set to 2 ** sourceWidth to allow some flexibility.
 2023-03-29 14:02:41 -07:00