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Re-enable coalescer in TLRAMCoalescerLoggerTest

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Now that the driver and logger are working (kinda).
This commit is contained in:
Hansung Kim
2023-04-20 21:11:12 -07:00
parent b2ab45f5e2
commit 7e405b5355
1 changed files with 5 additions and 6 deletions
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11
src/main/scala/tilelink/Coalescing.scala
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@@ -593,7 +593,7 @@ class MemTraceDriver(numLanes: Int = 4, filename: String = "vecadd.core1.thread4
val clientParam = Seq(
TLMasterParameters.v1(
name = "MemTraceDriver" + i.toString,
sourceId = IdRange(0, 0x1000)
sourceId = IdRange(0, 0x10)
// visibility = Seq(AddressSet(0x0000, 0xffffff))
)
)
@@ -972,10 +972,10 @@ object TracePrintf {
class TLRAMCoalescerLogger(implicit p: Parameters) extends LazyModule {
// TODO: use parameters for numLanes
val numLanes = 4
// val coal = LazyModule(new CoalescingUnit(numLanes))
val coal = LazyModule(new CoalescingUnit(numLanes))
val driver = LazyModule(new MemTraceDriver(numLanes))
val logger = LazyModule(new MemTraceLogger(numLanes))
val rams = Seq.fill(numLanes)( // +1 for coalesced edge
val logger = LazyModule(new MemTraceLogger(numLanes + 1))
val rams = Seq.fill(numLanes + 1)( // +1 for coalesced edge
LazyModule(
// NOTE: beatBytes here sets the data bitwidth of the upstream TileLink
// edges globally, by way of Diplomacy communicating the TL slave
@@ -984,8 +984,7 @@ class TLRAMCoalescerLogger(implicit p: Parameters) extends LazyModule {
)
)
// logger.node :=* coal.node :=* driver.node
logger.node :=* driver.node
logger.node :=* coal.node :=* driver.node
rams.foreach { r => r.node := logger.node }
lazy val module = new Impl