Hansung Kim 41d520a991 Log both request and response in trace logger
Inside DPI code, have a vector of unique_ptrs that act as handles to multiple
different trace logger instances.  Each logger instance is instantiated in a
single instance of the Verilog module, and multiple of these Verilog modules may
be instantiated in the Chisel module (see simReq and simResp in MemTraceLogger).
2023-04-17 18:10:13 -07:00
2023-03-27 14:38:02 -07:00
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Scala 91.6%
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