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b53711965ed642d74c1b9b5e3416a7df1b346b3e
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Hansung Kim b53711965e Connect TL edge data to SimMemTraceLogger 
TODO: since TileLink rounds all address down to a multiple of its beat
size (8 in the current code), we can't directly compare the memory trace
input to its output.  Need to take masks into account.
2023-04-10 20:24:27 -07:00
src
Connect TL edge data to SimMemTraceLogger
2023-04-10 20:24:27 -07:00
.scalafmt.conf
Add .scalafmt.conf
2023-03-27 14:38:02 -07:00
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Scala 91.6%
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Verilog 3.6%
Makefile 0.9%