Set TL size according to trace from driver
Mask will be set accordingly by the TL generator methods (Get/Put).
This commit is contained in:
@@ -656,21 +656,29 @@ class MemTraceDriverImp(outer: MemTraceDriver, numLanes: Int, traceFile: String)
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(outer.laneNodes zip laneReqs).foreach { case (node, req) =>
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val (tlOut, edge) = node.out(0)
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val size = 4.U // TODO: get proper size from the trace
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val (plegal, pbits) = edge.Put(
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fromSource = sourceIdCounter,
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toAddress = hashToValidPhyAddr(req.address),
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lgSize = Log2(size),
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lgSize = req.size, // trace line already holds log2(size)
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data = req.data
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)
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val (glegal, gbits) = edge.Get(
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fromSource = sourceIdCounter,
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toAddress = hashToValidPhyAddr(req.address),
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lgSize = Log2(size)
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lgSize = req.size
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)
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val legal = Mux(req.is_store, plegal, glegal)
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val bits = Mux(req.is_store, pbits, gbits)
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when(tlOut.a.valid) {
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printf(
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"Get(): addr=%x, size=%x, mask=%x\n",
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tlOut.a.bits.address,
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tlOut.a.bits.size,
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tlOut.a.bits.mask
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);
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}
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assert(legal, "illegal TL req gen")
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tlOut.a.valid := req.valid
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tlOut.a.bits := bits
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@@ -772,8 +780,8 @@ class MemTraceLogger(numLanes: Int = 4, filename: String = "vecadd.core1.thread4
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req.address := tlIn.a.bits.address
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req.data := tlIn.a.bits.data
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req.is_store := false.B
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when(tlIn.a.bits.opcode === 0.U || tlIn.a.bits.opcode === 1.U) {
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// 0: PutFullData, 1: PutPartialData
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when(tlIn.a.bits.opcode === 0.U) {
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// 0: PutFullData, 1: PutPartialData but we don't support it
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req.is_store := true.B
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}.elsewhen(tlIn.a.bits.opcode === 4.U) {
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// 4: Get
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@@ -784,10 +792,6 @@ class MemTraceLogger(numLanes: Int = 4, filename: String = "vecadd.core1.thread4
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}
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req.size := tlIn.a.bits.size
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when(req.valid) {
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printf("======== MemTraceLogger: req.size=%d\n", req.size)
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}
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// responses on TL D channel
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// TODO
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}
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