Fix verilog lint error

2023-04-10 20:37:26 -07:00
parent b53711965e
commit dca52ace0b
1 changed files with 1 additions and 1 deletions
--- a/src/main/resources/vsrc/SimMemTrace.v
+++ b/src/main/resources/vsrc/SimMemTrace.v
@@ -41,7 +41,7 @@ module SimMemTrace #(parameter FILENAME = "undefined", NUM_LANES = 4) (
  longint __in_address[NUM_LANES-1:0];

  bit __in_is_store[NUM_LANES-1:0];
-  int __in_store_mask [NUM_LANES-1:0];
+  logic [`MASK_WIDTH-1:0] __in_store_mask [NUM_LANES-1:0];
  longint __in_data[NUM_LANES-1:0];

  bit __in_finished;