Log both request and response in trace logger
Inside DPI code, have a vector of unique_ptrs that act as handles to multiple different trace logger instances. Each logger instance is instantiated in a single instance of the Verilog module, and multiple of these Verilog modules may be instantiated in the Chisel module (see simReq and simResp in MemTraceLogger).
This commit is contained in:
Hansung Kim
@@ -28,10 +28,11 @@ public:
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class MemTraceWriter {
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public:
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MemTraceWriter(const std::string &filename);
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MemTraceWriter(const bool is_response, const std::string &filename);
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~MemTraceWriter();
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void write_line_to_trace(const MemTraceLine line);
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bool is_response;
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FILE *outfile;
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};
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@@ -45,8 +46,9 @@ extern "C" void memtrace_query(unsigned char trace_read_ready,
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int *trace_read_size,
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unsigned long *trace_read_data,
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unsigned char *trace_read_finished);
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extern "C" void memtracelogger_init(const char *filename);
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extern "C" void memtracelogger_log(unsigned char trace_log_valid,
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extern "C" int memtracelogger_init(int is_response, const char *filename);
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extern "C" void memtracelogger_log(int handle,
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unsigned char trace_log_valid,
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unsigned long trace_log_cycle,
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unsigned long trace_log_address,
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int trace_log_lane_id,
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@@ -1,19 +1,23 @@
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#ifndef NO_VPI
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#include <vpi_user.h>
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#include <svdpi.h>
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#include <vpi_user.h>
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#endif
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#include <string>
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#include <cstring>
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#include <cstdio>
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#include <cassert>
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#include <memory>
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#include <unistd.h>
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#include "SimMemTrace.h"
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#include <cassert>
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#include <cstdio>
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#include <cstring>
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#include <memory>
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#include <string>
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#include <unistd.h>
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// Global singleton instance
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static std::unique_ptr<MemTraceWriter> logger;
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// Contains handle for every logger that is instantiated per Verilog module
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// instance
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static std::vector<std::unique_ptr<MemTraceWriter>> loggers;
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MemTraceWriter::MemTraceWriter(const bool is_response,
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const std::string &filename) {
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this->is_response = is_response;
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MemTraceWriter::MemTraceWriter(const std::string &filename) {
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char cwd[4096];
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if (getcwd(cwd, sizeof(cwd))) {
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printf("MemTraceWriter: current working dir: %s\n", cwd);
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@@ -36,16 +40,17 @@ void MemTraceWriter::write_line_to_trace(const MemTraceLine line) {
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line.address, line.data, (1u << line.log_data_size));
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}
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extern "C" void memtracelogger_init(const char *filename) {
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// Returns the "handle" ID for this particular logger instance.
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extern "C" int memtracelogger_init(int is_response, const char *filename) {
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#ifndef NO_VPI
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s_vpi_vlog_info info;
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if (!vpi_get_vlog_info(&info)) {
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fprintf(stderr, "fatal: failed to get plusargs from VCS\n");
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exit(1);
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}
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const char* TRACEFILENAME_PLUSARG = "+memtracefile=";
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const char *TRACEFILENAME_PLUSARG = "+memtracefile=";
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for (int i = 0; i < info.argc; i++) {
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char* input_arg = info.argv[i];
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char *input_arg = info.argv[i];
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if (strncmp(input_arg, TRACEFILENAME_PLUSARG,
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strlen(TRACEFILENAME_PLUSARG)) == 0) {
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filename = input_arg + strlen(TRACEFILENAME_PLUSARG);
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@@ -54,20 +59,24 @@ extern "C" void memtracelogger_init(const char *filename) {
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}
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#endif
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printf("memtrace_init: filename=[%s]\n", filename);
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int handle = loggers.size();
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loggers.emplace_back(std::make_unique<MemTraceWriter>(is_response, filename));
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logger = std::make_unique<MemTraceWriter>(filename);
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printf("memtracelogger_init: handle=%d, is_response=%d, filename=[%s]\n",
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handle, is_response, filename);
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return handle;
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}
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// This is used to log both TileLink A and D channels.
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// TODO: accept core_id as well
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extern "C" void memtracelogger_log(unsigned char trace_log_valid,
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unsigned long trace_log_cycle,
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unsigned long trace_log_address,
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int trace_log_lane_id,
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unsigned char trace_log_is_store,
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int trace_log_size,
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unsigned long trace_log_data,
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unsigned char *trace_log_ready) {
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extern "C" void
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memtracelogger_log(int handle,
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unsigned char trace_log_valid, unsigned long trace_log_cycle,
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unsigned long trace_log_address, int trace_log_lane_id,
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unsigned char trace_log_is_store, int trace_log_size,
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unsigned long trace_log_data,
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unsigned char *trace_log_ready) {
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// printf("memtrace_query(cycle=%ld, tid=%d)\n", trace_read_cycle,
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// trace_read_lane_id);
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*trace_log_ready = 1;
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@@ -77,8 +86,7 @@ extern "C" void memtracelogger_log(unsigned char trace_log_valid,
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}
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printf("%s: [%lu] valid: address=%lx, tid=%u, size=%d\n", __func__,
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trace_log_cycle, trace_log_address, trace_log_lane_id,
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trace_log_size);
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trace_log_cycle, trace_log_address, trace_log_lane_id, trace_log_size);
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MemTraceLine line{.valid = (trace_log_valid == 1),
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.cycle = static_cast<long>(trace_log_cycle),
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@@ -89,5 +97,7 @@ extern "C" void memtracelogger_log(unsigned char trace_log_valid,
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.data = trace_log_data,
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.log_data_size = trace_log_size};
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assert(0 <= handle && handle < loggers.size() && "wrong trace logger handle");
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auto logger = loggers[handle].get();
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logger->write_line_to_trace(line);
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}
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100
src/main/resources/vsrc/SimMemTraceLogger.v
Normal file
100
src/main/resources/vsrc/SimMemTraceLogger.v
Normal file
@@ -0,0 +1,100 @@
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// FIXME hardcoded
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`define DATA_WIDTH 64
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`define MAX_NUM_LANES 32
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`define LOGSIZE_WIDTH 32
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import "DPI-C" function int memtracelogger_init(
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input bit is_response,
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input string filename
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);
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// Make sure to sync the parameters for:
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// (1) import "DPI-C" declaration
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// (2) C function declaration
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// (3) DPI function calls inside initial/always blocks
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import "DPI-C" function void memtracelogger_log
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(
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input int handle,
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input bit trace_log_valid,
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input longint trace_log_cycle,
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input longint trace_log_address,
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input int trace_log_tid,
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input bit trace_log_is_store,
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input int trace_log_size,
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input longint trace_log_data,
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output bit trace_log_ready
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);
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module SimMemTraceLogger #(parameter
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IS_RESPONSE = 0,
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FILENAME = "undefined",
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NUM_LANES = 4) (
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input clock,
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input reset,
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// NOTE: LSB is lane 0
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input [NUM_LANES-1:0] trace_log_valid,
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input [`DATA_WIDTH*NUM_LANES-1:0] trace_log_address,
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input [NUM_LANES-1:0] trace_log_is_store,
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input [`LOGSIZE_WIDTH*NUM_LANES-1:0] trace_log_size,
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input [`DATA_WIDTH*NUM_LANES-1:0] trace_log_data,
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output trace_log_ready
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);
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int logger_handle;
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bit __in_ready;
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// cycle_counter will start off right after reset is deasserted which should
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// synchronize itself with SimMemTrace.cycle_counter
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reg [`DATA_WIDTH-1:0] cycle_counter;
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wire [`DATA_WIDTH-1:0] next_cycle_counter;
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assign next_cycle_counter = cycle_counter + 1'b1;
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// wires going into the DPC
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wire __valid [NUM_LANES-1:0];
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wire [`DATA_WIDTH-1:0] __address [NUM_LANES-1:0];
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wire __is_store [NUM_LANES-1:0];
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wire [`LOGSIZE_WIDTH-1:0] __size [NUM_LANES-1:0];
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wire [`DATA_WIDTH-1:0] __data [NUM_LANES-1:0];
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assign trace_log_ready = __in_ready;
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genvar g;
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generate
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for (g = 0; g < NUM_LANES; g = g + 1) begin
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// LSB is lane 0
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assign __valid[g] = trace_log_valid[g];
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assign __address[g] = trace_log_address[`DATA_WIDTH*(g+1)-1:`DATA_WIDTH*g];
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assign __is_store[g] = trace_log_is_store[g];
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assign __size[g] = trace_log_size[`LOGSIZE_WIDTH*(g+1)-1:`LOGSIZE_WIDTH*g];
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assign __data[g] = trace_log_data[`DATA_WIDTH*(g+1)-1:`DATA_WIDTH*g];
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end
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endgenerate
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initial begin
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/* $value$plusargs("uartlog=%s", __uartlog); */
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logger_handle = memtracelogger_init(IS_RESPONSE, FILENAME);
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end
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always @(posedge clock) begin
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if (reset) begin
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__in_ready = 1'b1;
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cycle_counter <= `DATA_WIDTH'b0;
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end else begin
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cycle_counter <= next_cycle_counter;
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for (integer tid = 0; tid < NUM_LANES; tid = tid + 1) begin
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memtracelogger_log(
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logger_handle,
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__valid[tid],
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cycle_counter,
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__address[tid],
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tid,
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__is_store[tid],
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__size[tid],
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__data[tid],
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__in_ready
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);
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end
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end
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end
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endmodule
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@@ -747,7 +747,11 @@ class SimMemTrace(filename: String, numLanes: Int)
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addResource("/csrc/SimMemTrace.h")
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}
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class MemTraceLogger(numLanes: Int = 4, filename: String = "vecadd.core1.thread4.out.trace")(implicit
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class MemTraceLogger(
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numLanes: Int = 4,
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reqFilename: String = "vecadd.core1.thread4.logger.req.trace",
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respFilename: String = "vecadd.core1.thread4.logger.resp.trace"
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)(implicit
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p: Parameters
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) extends LazyModule {
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val node = TLIdentityNode()
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@@ -775,98 +779,152 @@ class MemTraceLogger(numLanes: Int = 4, filename: String = "vecadd.core1.thread4
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lazy val module = new Impl
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class Impl extends LazyModuleImp(this) {
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val sim = Module(new SimMemTraceLogger(filename, numLanes))
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sim.io.clock := clock
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sim.io.reset := reset.asBool
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val simReq = Module(new SimMemTraceLogger(false, reqFilename, numLanes))
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val simResp = Module(new SimMemTraceLogger(true, respFilename, numLanes))
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simReq.io.clock := clock
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simReq.io.reset := reset.asBool
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simResp.io.clock := clock
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simResp.io.reset := reset.asBool
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val laneReqs = Wire(Vec(numLanes, new TraceReq))
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val laneResps = Wire(Vec(numLanes, new TraceReq))
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assert(
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numLanes == node.in.length,
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"`numLanes` does not match the number of TL edges connected to the MemTraceLogger"
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)
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def tlAOpcodeIsStore(opcode: UInt): Bool = {
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// 0: PutFullData, 1: PutPartialData but we don't support it
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// 4: Get
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assert(opcode === 0.U || opcode === 4.U, "unhandled TL A opcode found")
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opcode === 0.U
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}
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def tlDOpcodeIsStore(opcode: UInt): Bool = {
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// 0: AccessAck (Put), 1: AccessAckData (Get or Atomic)
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// See Table 13 of spec 1.8.1
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assert(opcode === 0.U || opcode === 1.U, "unhandled TL D opcode found")
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opcode === 0.U
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}
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// snoop on the TileLink edges to log traffic
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((node.in zip node.out) zip laneReqs).foreach { case (((tlIn, _), (tlOut, _)), req) =>
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tlOut.a <> tlIn.a
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tlIn.d <> tlOut.d
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((node.in zip node.out) zip (laneReqs zip laneResps)).foreach {
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case (((tlIn, _), (tlOut, _)), (req, resp)) =>
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tlOut.a <> tlIn.a
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tlIn.d <> tlOut.d
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// requests on TL A channel
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//
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req.valid := tlIn.a.valid
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req.size := tlIn.a.bits.size
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def tlOpcodeIsStore(opcode: UInt): Bool = {
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// 0: PutFullData, 1: PutPartialData but we don't support it
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// 4: Get
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assert(opcode === 0.U || opcode === 4.U, "unhandled TL opcode found in MemTraceLogger")
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tlIn.a.bits.opcode === 0.U
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}
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req.is_store := tlOpcodeIsStore(tlIn.a.bits.opcode)
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// TL always carries the exact unaligned address that the client
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// originally requested, so no postprocessing required
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req.address := tlIn.a.bits.address
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// requests on TL A channel
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//
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req.valid := tlIn.a.valid
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req.size := tlIn.a.bits.size
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req.is_store := tlAOpcodeIsStore(tlIn.a.bits.opcode)
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// TL always carries the exact unaligned address that the client
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// originally requested, so no postprocessing required
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req.address := tlIn.a.bits.address
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// TL data
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//
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// When tlIn.a.bits.size is smaller than the data bus width, need to
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// figure out which byte lanes we actually accessed so that
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// we can write that to the memory trace.
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// See Section 4.5 Byte Lanes in spec 1.8.1
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// TL data
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//
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// When tlIn.a.bits.size is smaller than the data bus width, need to
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// figure out which byte lanes we actually accessed so that
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// we can write that to the memory trace.
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// See Section 4.5 Byte Lanes in spec 1.8.1
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// This assert only holds true for PutFullData and not PutPartialData,
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// where HIGH bits in the mask may not be contiguous.
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assert(
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PopCount(tlIn.a.bits.mask) === (1.U << tlIn.a.bits.size),
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"mask HIGH bits do not match the TL size. This should have been handled by the TL generator logic"
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)
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val trailingZerosInMask = trailingZeros(tlIn.a.bits.mask)
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val mask = ~((~0.U) << (trailingZerosInMask * 8.U))
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req.data := mask & (tlIn.a.bits.data >> (trailingZerosInMask * 8.U))
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when(req.valid) {
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TracePrintf(
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"MemTraceLogger",
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tlIn.a.bits.address,
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tlIn.a.bits.size,
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tlIn.a.bits.mask,
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req.is_store,
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tlIn.a.bits.data,
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req.data
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// This assert only holds true for PutFullData and not PutPartialData,
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// where HIGH bits in the mask may not be contiguous.
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assert(
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PopCount(tlIn.a.bits.mask) === (1.U << tlIn.a.bits.size),
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"mask HIGH bits do not match the TL size. This should have been handled by the TL generator logic"
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)
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}
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val trailingZerosInMask = trailingZeros(tlIn.a.bits.mask)
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val mask = ~((~0.U) << (trailingZerosInMask * 8.U))
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req.data := mask & (tlIn.a.bits.data >> (trailingZerosInMask * 8.U))
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// responses on TL D channel
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// TODO
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when(req.valid) {
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TracePrintf(
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"MemTraceLogger",
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tlIn.a.bits.address,
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tlIn.a.bits.size,
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tlIn.a.bits.mask,
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req.is_store,
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tlIn.a.bits.data,
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req.data
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)
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}
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// responses on TL D channel
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//
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resp.valid := tlOut.d.valid
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resp.size := tlOut.d.bits.size
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resp.is_store := tlDOpcodeIsStore(tlOut.d.bits.opcode)
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// NOTE: TL D channel doesn't carry address nor mask, so there's no easy
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// way to figure out which bytes the master actually use. Since we
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// don't care too much about addresses in the trace anyway, just store
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// the entire bits.
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resp.address := 0.U
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resp.data := tlOut.d.bits.data
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}
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// clunky workaround of the fact that Chisel doesn't allow partial
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// assignment to a bitfield range of a wide signal.
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val laneValid = Wire(Vec(numLanes, Bool()))
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val laneAddress = Wire(Vec(numLanes, chiselTypeOf(laneReqs(0).address)))
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val laneIsStore = Wire(Vec(numLanes, chiselTypeOf(laneReqs(0).is_store)))
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val laneSize = Wire(Vec(numLanes, chiselTypeOf(laneReqs(0).size)))
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val laneData = Wire(Vec(numLanes, chiselTypeOf(laneReqs(0).data)))
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laneReqs.zipWithIndex.foreach { case (req, i) =>
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laneValid(i) := req.valid
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laneAddress(i) := req.address
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laneIsStore(i) := req.is_store
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laneSize(i) := req.size
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laneData(i) := req.data
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def flattenTrace(traceLogIO: Bundle with HasTraceReq, perLane: Vec[TraceReq]) = {
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val laneValid = Wire(Vec(numLanes, Bool()))
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val laneAddress = Wire(Vec(numLanes, chiselTypeOf(perLane(0).address)))
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val laneIsStore = Wire(Vec(numLanes, chiselTypeOf(perLane(0).is_store)))
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val laneSize = Wire(Vec(numLanes, chiselTypeOf(perLane(0).size)))
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val laneData = Wire(Vec(numLanes, chiselTypeOf(perLane(0).data)))
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perLane.zipWithIndex.foreach { case (req, i) =>
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laneValid(i) := req.valid
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laneAddress(i) := req.address
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laneIsStore(i) := req.is_store
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laneSize(i) := req.size
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laneData(i) := req.data
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}
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// flatten per-lane signals to the Verilog blackbox input
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traceLogIO.valid := laneValid.asUInt
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traceLogIO.address := laneAddress.asUInt
|
||||
traceLogIO.is_store := laneIsStore.asUInt
|
||||
traceLogIO.size := laneSize.asUInt
|
||||
traceLogIO.data := laneData.asUInt
|
||||
}
|
||||
// flatten per-lane signals to the Verilog blackbox input
|
||||
sim.io.trace_log.valid := laneValid.asUInt
|
||||
sim.io.trace_log.address := laneAddress.asUInt
|
||||
sim.io.trace_log.is_store := laneIsStore.asUInt
|
||||
sim.io.trace_log.size := laneSize.asUInt
|
||||
sim.io.trace_log.data := laneData.asUInt
|
||||
|
||||
assert(sim.io.trace_log.ready === true.B, "MemTraceLogger is expected to be always ready")
|
||||
flattenTrace(simReq.io.trace_log, laneReqs)
|
||||
flattenTrace(simResp.io.trace_log, laneResps)
|
||||
|
||||
assert(simReq.io.trace_log.ready === true.B, "MemTraceLogger is expected to be always ready")
|
||||
assert(simResp.io.trace_log.ready === true.B, "MemTraceLogger is expected to be always ready")
|
||||
|
||||
// val laneValid = Wire(Vec(numLanes, Bool()))
|
||||
// val laneAddress = Wire(Vec(numLanes, chiselTypeOf(laneReqs(0).address)))
|
||||
// val laneIsStore = Wire(Vec(numLanes, chiselTypeOf(laneReqs(0).is_store)))
|
||||
// val laneSize = Wire(Vec(numLanes, chiselTypeOf(laneReqs(0).size)))
|
||||
// val laneData = Wire(Vec(numLanes, chiselTypeOf(laneReqs(0).data)))
|
||||
// laneReqs.zipWithIndex.foreach { case (req, i) =>
|
||||
// laneValid(i) := req.valid
|
||||
// laneAddress(i) := req.address
|
||||
// laneIsStore(i) := req.is_store
|
||||
// laneSize(i) := req.size
|
||||
// laneData(i) := req.data
|
||||
// }
|
||||
// // flatten per-lane signals to the Verilog blackbox input
|
||||
// simReq.io.trace_log.valid := laneValid.asUInt
|
||||
// simReq.io.trace_log.address := laneAddress.asUInt
|
||||
// simReq.io.trace_log.is_store := laneIsStore.asUInt
|
||||
// simReq.io.trace_log.size := laneSize.asUInt
|
||||
// simReq.io.trace_log.data := laneData.asUInt
|
||||
}
|
||||
}
|
||||
|
||||
class SimMemTraceLogger(filename: String, numLanes: Int)
|
||||
// MemTraceLogger is bidirectional. The DPI module tells itself if it's logging
|
||||
// the request stream or the response stream by `isResponse`. This distinction
|
||||
// is needed because the response trace file will not contain certain columns
|
||||
// such as address.
|
||||
class SimMemTraceLogger(isResponse: Boolean, filename: String, numLanes: Int)
|
||||
extends BlackBox(
|
||||
Map("FILENAME" -> filename, "NUM_LANES" -> numLanes)
|
||||
Map(
|
||||
"IS_RESPONSE" -> (if (isResponse) 1 else 0),
|
||||
"FILENAME" -> filename,
|
||||
"NUM_LANES" -> numLanes
|
||||
)
|
||||
)
|
||||
with HasBlackBoxResource {
|
||||
val io = IO(new Bundle {
|
||||
|
||||
Reference in New Issue
Block a user