Generate proper AccessAck/AccessAckData from response queue

src/main/resources/csrc/SimMemTraceLogger.cc

@@ -88,8 +88,8 @@ extern "C" void memtracelogger_log(int handle,
     return;
   }
 
-  printf("%s: [%lu] valid: address=%lx, tid=%u, size=%d\n", __func__,
-         trace_log_cycle, trace_log_address, trace_log_lane_id, trace_log_size);
+  // printf("%s: [%lu] valid: address=%lx, tid=%u, size=%d\n", __func__,
+  //        trace_log_cycle, trace_log_address, trace_log_lane_id, trace_log_size);
 
   MemTraceLine line{.valid = (trace_log_valid == 1),
                     .cycle = static_cast<long>(trace_log_cycle),

src/main/scala/tilelink/Coalescing.scala

@@ -193,12 +193,16 @@ class CoalescingUnitImp(outer: CoalescingUnit, numLanes: Int) extends LazyModule
 
       tlIn.d.valid := respQueue.io.deq(respQueueNoncoalPort).valid
       val respHead = respQueue.io.deq(respQueueNoncoalPort).bits
-      // TODO: AccessAckData for Get
-      val respBits = edgeIn.AccessAck(
+      val apBits = edgeIn.AccessAck(
         toSource = respHead.source,
-        lgSize = 0.U,
+        lgSize = respHead.size
+      )
+      val agBits = edgeIn.AccessAck(
+        toSource = respHead.source,
+        lgSize = respHead.size,
         data = respHead.data
       )
+      val respBits = Mux(respHead.isStore, apBits, agBits)
       tlIn.d.bits := respBits
 
       // Debug only