Eliminate unnecessary delay when invalidating head
When invalidate signal is given for queue head, that head should be gone immediately at the next cycle, regardless of what deq.ready was at the previous cycle.
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@@ -495,7 +495,7 @@ class CoalShiftQueue[T <: Data](
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else if (i == entries) false.B
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else Mux(io.invalidate(i), false.B, paddedValid(i))
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val shift = io.deq.ready || (used =/= 0.U) && !valid(0)
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val shift = io.deq.ready || (used =/= 0.U) && !paddedValidAfterInvalidate(0)
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for (i <- 0 until entries) {
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val wdata = if (i == entries - 1) io.enq.bits else Mux(!used(i + 1), io.enq.bits, elts(i + 1))
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val wen = Mux(
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@@ -1,7 +1,6 @@
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import chisel3._
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import chiseltest._
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import org.scalatest.flatspec.AnyFlatSpec
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import org.scalatest._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util.MultiPortQueue
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@@ -168,12 +167,11 @@ class CoalShiftQueueTest extends AnyFlatSpec with ChiselScalatestTester {
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// invalidate two entries at head
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c.io.invalidate.poke(0x3.U)
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c.clock.step()
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// 0x12 should have been dequeued now
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c.io.invalidate.poke(0x0.U)
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c.io.deq.ready.poke(false.B)
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// 0x12 should be dequeued now
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c.clock.step()
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// 0x34 should be dequeued now
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c.clock.step()
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// 0x34 should have been dequeued now
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c.io.deq.ready.poke(true.B)
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c.io.deq.valid.expect(true.B)
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c.io.deq.bits.expect(0x56.U)
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@@ -182,6 +180,25 @@ class CoalShiftQueueTest extends AnyFlatSpec with ChiselScalatestTester {
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c.io.deq.valid.expect(false.B)
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}
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}
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it should "overwrite invalidated tail when enqueuing" in {
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test(new CoalShiftQueue(UInt(8.W), 4)) { c =>
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c.io.invalidate.poke(0.U)
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// prepare
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c.io.deq.ready.poke(false.B)
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c.io.enq.ready.expect(true.B)
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c.io.enq.valid.poke(true.B)
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c.io.enq.bits.poke(0x12.U)
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c.clock.step()
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// invalidate and enqueue at the tail at the same time
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c.io.invalidate.poke(0x1.U)
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c.io.deq.ready.poke(false.B)
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c.io.enq.ready.expect(true.B)
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c.io.enq.valid.poke(true.B)
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c.io.enq.bits.poke(0x34.U)
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}
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}
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}
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class UncoalescingUnitTest extends AnyFlatSpec with ChiselScalatestTester {
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