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7e6ebb9e35eef7bdd63a525a171fc3c90e5f99a4
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Author SHA1 Message Date
Hansung Kim
7e6ebb9e35 Create SoC-integrated Config for Coalescer 
This requires config.addressWidth to be increased to 32.
FIXME: This breaks CoalescerUnitTest with unsatisfied requirement
`Link's max transfer (8) < List<...>'s beatBytes (32)`.
 2023-05-12 01:15:28 -07:00
Richard Yan
80ffc6cc73 write striping across banks 2023-05-12 00:31:28 -07:00
Richard Yan
4e4b993287 Merge branch 'graphics' of https://github.com/hansungk/rocket-chip into graphics 2023-05-11 21:50:42 -07:00
Hansung Kim
9b7080a852 Delete old inflight table unittest 2023-05-11 18:50:47 -07:00
Hansung Kim
226e1d2d84 Fix uncoalescer unittest even more 2023-05-11 18:36:09 -07:00
Hansung Kim
b95b59cce0 Fix uncoalescer unittest 2023-05-11 18:30:15 -07:00
Hansung Kim
df68bfec84 Remove module dependency for uncoalescer instantiation 
for easier unittesting. now builds.
 2023-05-11 18:20:19 -07:00
Richard Yan
f0a7fd852a WIP bank striping 2023-05-11 18:12:25 -07:00
Hansung Kim
0df3192882 Revamp uncoalescer IO 
Connect coalescer output directly to the uncoalescer at the toplevel, and do
table entry construction entirely inside the module.
WIP: unittest is very broken as a result of this.
 2023-05-11 17:31:51 -07:00
Hansung Kim
772deda9c2 Fix ChiselEnum experimental warning 2023-05-11 16:20:01 -07:00
Hansung Kim
0c8909cb43 scalafmt 2023-05-11 16:11:39 -07:00
Hansung Kim
7fa6be4a8b Use case class for noncoal/coal bundles 
don't know what they really do, but they look fancy
 2023-05-11 15:56:30 -07:00
Hansung Kim
406f90b633 De-duplicate equivalent Request bundles using NonCoal/Coal variants 2023-05-11 15:55:15 -07:00
Hansung Kim
5fed3ef823 Generalize Req/RespQueueEntry into Response/Request bundle 2023-05-11 15:42:23 -07:00
Hansung Kim
300eff4f9a Fix misleading maxSize param in Req/RespQueueEntry 2023-05-10 23:25:57 -07:00
Vamber Yang
4f31cad513 Merge remote-tracking branch 'origin/graphics' into local-dev-branch 2023-05-10 19:02:16 -07:00
Vamber Yang
1633371f6f Coalescer XBar, a design overhaul from CoalArbiter, the best way to implement the 'arbiter' functionality is to implement as a TLXbar with different arbitration policy (RR + PO) 2023-05-10 18:59:36 -07:00
Hansung Kim
b48ab70e67 Fix assertion falsely firing on invalid 2023-05-10 00:26:25 -07:00
Hansung Kim
19d378dc3a Fix sourceGen unasserted firrtl error 2023-05-10 00:13:04 -07:00
Hansung Kim
6032d79ead Implement proper source gen 2023-05-09 23:46:11 -07:00
Hansung Kim
1886aefcc1 Parameterize tracefile has_source from Config 2023-05-09 22:22:27 -07:00
Hansung Kim
89398cdc3d Fix CanHaveMemtraceCore not setting numLane 2023-05-09 19:02:03 -07:00
Hansung Kim
2ade624343 Fix backpressure handling in MemTraceDriver when attached to SoC 2023-05-09 17:54:39 -07:00
Hansung Kim
f52492c56b Create separate config for memtrace core 2023-05-09 13:07:45 -07:00
Richard Yan
7bd9fd43f8 Merge branch 'graphics' of https://github.com/hansungk/rocket-chip into graphics 2023-05-09 09:37:59 -07:00
Richard Yan
bce2c6230f more test fixes 2023-05-09 09:36:29 -07:00
Hansung Kim
9059d1e436 Misc doc 2023-05-08 20:35:40 -07:00
Hansung Kim
fd0d09691b Create separate Configs for synthesizable dummy testbenches 2023-05-08 17:51:24 -07:00
Hansung Kim
f6be54a122 Set up proper Config system for numLanes 
TODO: tracefilename should not really be inside SIMTCoreParam.
 2023-05-08 17:34:29 -07:00
Vamber Yang
25c0b6cfa5 CoalArbiter RTL written, verification WIP, merged changes from graphics 2023-05-08 16:57:26 -07:00
Vamber Yang
9c2a55ae79 CoalArbiter RTL implementation first draft, verification WIP 2023-05-08 16:52:45 -07:00
Hansung Kim
3fae0b2c7a Use priority encoder for chooseLeaderIdx 2023-05-08 15:18:45 -07:00
Hansung Kim
2d4e28e862 Use WithoutTLMonitors to slightly speed up chiseltests 2023-05-08 14:38:15 -07:00
Hansung Kim
54a3e3cf72 Initiate memtrace DPI only when trace_read_ready 
This is required because otherwise we might overwrite into
the Verilog registers that contain a valid trace line that
was missed by downstream when it was not ready.  Basically
whenever trace_read_cycle stalls, we also want to stall
__in_* registers.
 2023-05-08 14:34:52 -07:00
Hansung Kim
2e219ea15a Connect CoalShiftQueue enq.ready to upstream TL.ready 
Now CoalShiftQueue can properly stall memtrace driver.
 2023-05-08 14:27:54 -07:00
Hansung Kim
8cdbc81bdd Only write in MemTraceLogger when TL fire 
Without this we log extraneous lines that were valid but not transacted with the
downstream as it was not ready, which affects validity of memtrace testing.
 2023-05-08 14:26:05 -07:00
Hansung Kim
6755cb3eec Lax traceReadCycle advancing logic 
Trying to advance trace cycle while downstream is blocking
is tricky because DPI call is synchronous, and that gives
timing difference between the line we have fired to downstream
and the current cycle counter we maintain.
Just stall the counter whenever downstream is not ready
for now.
 2023-05-08 00:49:30 -07:00
Hansung Kim
6b97b77572 Revert SimMemTrace.v to use posedge clock 
Doing function calls inside @(*) causes lint errors.  Instead, remove
staging registers to eliminate 1 cycle latency between DPI call and
when output is visible to Chisel.
 2023-05-08 00:14:48 -07:00
Vamber Yang
99d1e45a49 CoalArbiter RTL outgoing side implementation 2023-05-08 00:05:16 -07:00
Hansung Kim
f7df5045d4 Respect downstream TL A ready in MemTraceDriver 2023-05-07 23:55:54 -07:00
Hansung Kim
ba600db7e4 Backport SimMemTrace fix 2023-05-07 23:54:49 -07:00
Hansung Kim
737a760fcd Enable coverage tests for chiseltest 2023-05-07 22:58:20 -07:00
Hansung Kim
15889d7667 Take filename from Configs for easier trace testing 2023-05-07 19:09:25 -07:00
Hansung Kim
c75eaaf727 Backport SimMemTrace 2023-05-07 18:38:26 -07:00
Hansung Kim
a6dbfc3901 Fix config for unittest 2023-05-07 18:38:23 -07:00
Hansung Kim
5e073f2dec Doc update 2023-05-07 18:36:29 -07:00
Richard Yan
d2e56be157 update unit tests for new timing behavior & config 2023-05-07 14:35:53 -07:00
Richard Yan
262a20c992 Merge branch 'graphics' of https://github.com/hansungk/rocket-chip into graphics 2023-05-07 02:34:11 -07:00
Richard Yan
86e7d3d60d numerous coalescer bug fixes + working unit test 2023-05-07 02:31:28 -07:00
Hansung Kim
2d4cd542c1 Backport SimMemTrace: non-chronological trace error 2023-05-06 23:21:08 -07:00