Commit Graph

21 Commits

Author SHA1 Message Date
Colin Schmidt
e007b49179 bump rocket-chip to enable large memory spaces (#76)
* bump rocket-chip to enable large memory spaces

* Tests pass with write mask bug fix

* fix verisim build

* Update to point to rocket-chip on master

* bump rocket-chip and barstools

This fixes the analog chisel bug and
incorporates the firrtl MDF support (h/t John Wright)
2019-05-14 10:22:31 -07:00
Colin Schmidt
00d8e04d93 Use SBT for barstools instead of jars (#66)
* Use SBT for barstools instead of jars

* Make MACROCOMPILER_MODE a variable

This eases the downstream maintenance burden where `MACROCOMPILER_MODE` is not simply `--mode synflops`
2019-04-16 21:15:00 -07:00
John Wright
5be8de1288 Build additional annos and fir (#64) 2019-03-29 14:00:52 -07:00
Colin Schmidt
3425def36b Bumps barstools and fixes build system after (#63)
Barstools now handles annotations correctly.
This means that the blackboxresources for the harness
and top are different and need to be merged in the build system.
We also add all Sim*.cc files to default resources as our new emulator
demands. We then remove them from the harness .f file to avoid having
to detect which ones to include selectively.
2019-03-28 11:47:32 -07:00
Colin Schmidt
cf9136de4a backport ucb-bar/project-template/pull/59 2019-03-28 09:36:16 -07:00
Paul Rigge
8a522ba404 Fix some build system problems.
1) Bump testchipip to include forgotten commit
2) Add some support for generating VCS files
3) Fix some makefile deps
2019-03-06 22:10:31 -08:00
Paul Rigge
ddf3159d61 Bump rocket, make possible to use published deps (#47)
* Use published rocketchip

* Simulator works!

* Gitignore was masking csrc

* Fix broken submodules

* Update gitignore

* Fix things up

* Some more cleanup

* Clean up so that using maven works

* Incorporate feedback

* Oops

* Add workaround for some of csrc

* Forgot dtm and jtag

* Make name better and add comment

* Extraneous comment

* Fix includes.

After running a clean build, I realized old build state was masking this
problem. verisim/csrc needs to be in the include path until we find a more
permanent solution to our problem.

* Add target to generate verilator-specific files.

* Ignore DS_Store

* Generate bootrom from testchipip

* Oops

* Add extraneous rocket-dsptools reference
2019-03-06 18:22:21 -08:00
John Wright
acd76e5410 Adding barstools to separate the top from harness and to generate the
memories as external modules, which makes VLSI flows easier to plug in.
2019-02-13 21:13:08 -08:00
Edward Wang
d48587b671 Update project-template for testchipip master 2018-11-02 12:05:36 -07:00
Albert Ou
048492e54c mk: Ensure that FIRRTL jar has updated timestamp
SBT does not replace $(ROCKETCHIP_DIR)/firrtl/utils/bin/firrtl.jar if
compilation produces the same results.
2018-10-02 17:43:51 -07:00
Albert Ou
220aeea4c8 Bump rocket-chip
- Update Scala version to 2.12.4; work around SBT multi-project idiosyncrasies
- Remove HasSystemErrorSlave
2018-09-29 13:30:07 -07:00
Howard Mao
a3684d01dd use build.sbt instead of jar files to collect packages 2018-05-03 17:09:59 -07:00
Howard Mao
4c8c6e29f0 update rocket-chip again 2018-04-18 17:13:07 -07:00
Howard Mao
7e70e3525f move bootrom to testchipip 2018-04-17 15:13:47 -07:00
Howard Mao
d88c2fa84f add regression tests to makefile 2018-02-23 13:48:45 -08:00
Howard Mao
073c16961e make sure annotations are generated and carried through to verilog elaboration 2018-02-23 11:50:33 -08:00
Howard Mao
1dfe9b1c9f bump rocket-chip and fix deprecated code in testchipip.GeneratorApp 2018-02-23 11:46:40 -08:00
Howard Mao
e4a4046375 get RV32 working 2017-11-03 18:00:27 -07:00
Colin Schmidt
24cb846812 Build firrtl first so we dont get that weird error 2017-07-13 16:58:52 -07:00
Howard Mao
062d443863 upgrade to latest rocket-chip 2017-05-25 12:55:52 -07:00
Howard Mao
7074420aba initial commit 2016-10-21 16:03:26 -07:00